mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-11-10 01:10:48 +00:00
49ad5d5dd5
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206313 91177308-0d34-0410-b5e6-96231b3b80d8
417 lines
9.2 KiB
LLVM
417 lines
9.2 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
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;; Test various conversions.
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define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: trunc_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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; CHECK: str w2, [sp, #8]
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; CHECK: str x3, [sp]
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; CHECK: ldr x3, [sp]
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; CHECK: mov x0, x3
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; CHECK: str w0, [sp, #8]
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; CHECK: ldr w0, [sp, #8]
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; CHECK: strh w0, [sp, #12]
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; CHECK: ldrh w0, [sp, #12]
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; CHECK: strb w0, [sp, #15]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: uxtb w0, w0
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; CHECK: add sp, sp, #16
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; CHECK: ret
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%a.addr = alloca i8, align 1
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%b.addr = alloca i16, align 2
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%c.addr = alloca i32, align 4
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%d.addr = alloca i64, align 8
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store i8 %a, i8* %a.addr, align 1
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store i16 %b, i16* %b.addr, align 2
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store i32 %c, i32* %c.addr, align 4
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store i64 %d, i64* %d.addr, align 8
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%tmp = load i64* %d.addr, align 8
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%conv = trunc i64 %tmp to i32
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store i32 %conv, i32* %c.addr, align 4
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%tmp1 = load i32* %c.addr, align 4
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%conv2 = trunc i32 %tmp1 to i16
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store i16 %conv2, i16* %b.addr, align 2
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%tmp3 = load i16* %b.addr, align 2
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%conv4 = trunc i16 %tmp3 to i8
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store i8 %conv4, i8* %a.addr, align 1
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%tmp5 = load i8* %a.addr, align 1
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%conv6 = zext i8 %tmp5 to i32
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ret i32 %conv6
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}
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define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: zext_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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; CHECK: str w2, [sp, #8]
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; CHECK: str x3, [sp]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: uxtb w0, w0
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; CHECK: strh w0, [sp, #12]
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; CHECK: ldrh w0, [sp, #12]
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; CHECK: uxth w0, w0
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; CHECK: str w0, [sp, #8]
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; CHECK: ldr w0, [sp, #8]
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; CHECK: uxtw x3, w0
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; CHECK: str x3, [sp]
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; CHECK: ldr x0, [sp], #16
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; CHECK: ret
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%a.addr = alloca i8, align 1
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%b.addr = alloca i16, align 2
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%c.addr = alloca i32, align 4
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%d.addr = alloca i64, align 8
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store i8 %a, i8* %a.addr, align 1
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store i16 %b, i16* %b.addr, align 2
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store i32 %c, i32* %c.addr, align 4
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store i64 %d, i64* %d.addr, align 8
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%tmp = load i8* %a.addr, align 1
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%conv = zext i8 %tmp to i16
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store i16 %conv, i16* %b.addr, align 2
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%tmp1 = load i16* %b.addr, align 2
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%conv2 = zext i16 %tmp1 to i32
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store i32 %conv2, i32* %c.addr, align 4
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%tmp3 = load i32* %c.addr, align 4
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%conv4 = zext i32 %tmp3 to i64
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store i64 %conv4, i64* %d.addr, align 8
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%tmp5 = load i64* %d.addr, align 8
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ret i64 %tmp5
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}
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define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
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entry:
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; CHECK: @zext_i1_i32
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; CHECK: and w0, w0, #0x1
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%conv = zext i1 %a to i32
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ret i32 %conv;
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}
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define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
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entry:
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; CHECK: @zext_i1_i64
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; CHECK: and w0, w0, #0x1
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%conv = zext i1 %a to i64
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ret i64 %conv;
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}
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define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
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entry:
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; CHECK: sext_
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; CHECK: sub sp, sp, #16
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; CHECK: strb w0, [sp, #15]
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; CHECK: strh w1, [sp, #12]
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; CHECK: str w2, [sp, #8]
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; CHECK: str x3, [sp]
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; CHECK: ldrb w0, [sp, #15]
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; CHECK: sxtb w0, w0
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; CHECK: strh w0, [sp, #12]
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; CHECK: ldrh w0, [sp, #12]
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; CHECK: sxth w0, w0
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; CHECK: str w0, [sp, #8]
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; CHECK: ldr w0, [sp, #8]
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; CHECK: sxtw x3, w0
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; CHECK: str x3, [sp]
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; CHECK: ldr x0, [sp], #16
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; CHECK: ret
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%a.addr = alloca i8, align 1
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%b.addr = alloca i16, align 2
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%c.addr = alloca i32, align 4
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%d.addr = alloca i64, align 8
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store i8 %a, i8* %a.addr, align 1
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store i16 %b, i16* %b.addr, align 2
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store i32 %c, i32* %c.addr, align 4
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store i64 %d, i64* %d.addr, align 8
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%tmp = load i8* %a.addr, align 1
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%conv = sext i8 %tmp to i16
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store i16 %conv, i16* %b.addr, align 2
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%tmp1 = load i16* %b.addr, align 2
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%conv2 = sext i16 %tmp1 to i32
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store i32 %conv2, i32* %c.addr, align 4
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%tmp3 = load i32* %c.addr, align 4
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%conv4 = sext i32 %tmp3 to i64
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store i64 %conv4, i64* %d.addr, align 8
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%tmp5 = load i64* %d.addr, align 8
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ret i64 %tmp5
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}
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; Test sext i8 to i64
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define i64 @sext_2(i8 signext %a) nounwind ssp {
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entry:
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; CHECK: sext_2
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; CHECK: sxtb x0, w0
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%conv = sext i8 %a to i64
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ret i64 %conv
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}
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; Test sext i1 to i32
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define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i32
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; CHECK: sbfm w0, w0, #0, #0
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%conv = sext i1 %a to i32
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ret i32 %conv
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}
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; Test sext i1 to i16
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define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i16
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; CHECK: sbfm w0, w0, #0, #0
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%conv = sext i1 %a to i16
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ret i16 %conv
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}
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; Test sext i1 to i8
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define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
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entry:
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; CHECK: sext_i1_i8
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; CHECK: sbfm w0, w0, #0, #0
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%conv = sext i1 %a to i8
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ret i8 %conv
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}
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; Test fpext
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define double @fpext_(float %a) nounwind ssp {
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entry:
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; CHECK: fpext_
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; CHECK: fcvt d0, s0
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%conv = fpext float %a to double
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ret double %conv
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}
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; Test fptrunc
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define float @fptrunc_(double %a) nounwind ssp {
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entry:
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; CHECK: fptrunc_
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; CHECK: fcvt s0, d0
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%conv = fptrunc double %a to float
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ret float %conv
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}
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; Test fptosi
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define i32 @fptosi_ws(float %a) nounwind ssp {
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entry:
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; CHECK: fptosi_ws
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; CHECK: fcvtzs w0, s0
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%conv = fptosi float %a to i32
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ret i32 %conv
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}
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; Test fptosi
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define i32 @fptosi_wd(double %a) nounwind ssp {
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entry:
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; CHECK: fptosi_wd
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; CHECK: fcvtzs w0, d0
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%conv = fptosi double %a to i32
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ret i32 %conv
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}
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; Test fptoui
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define i32 @fptoui_ws(float %a) nounwind ssp {
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entry:
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; CHECK: fptoui_ws
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; CHECK: fcvtzu w0, s0
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%conv = fptoui float %a to i32
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ret i32 %conv
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}
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; Test fptoui
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define i32 @fptoui_wd(double %a) nounwind ssp {
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entry:
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; CHECK: fptoui_wd
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; CHECK: fcvtzu w0, d0
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%conv = fptoui double %a to i32
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ret i32 %conv
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}
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; Test sitofp
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define float @sitofp_sw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i1
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; CHECK: sbfm w0, w0, #0, #0
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; CHECK: scvtf s0, w0
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%conv = sitofp i1 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i8
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; CHECK: sxtb w0, w0
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; CHECK: scvtf s0, w0
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%conv = sitofp i8 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw_i16
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; CHECK: sxth w0, w0
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; CHECK: scvtf s0, w0
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%conv = sitofp i16 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sw(i32 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sw
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; CHECK: scvtf s0, w0
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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; Test sitofp
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define float @sitofp_sx(i64 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_sx
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; CHECK: scvtf s0, x0
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%conv = sitofp i64 %a to float
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ret float %conv
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}
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; Test sitofp
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define double @sitofp_dw(i32 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_dw
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; CHECK: scvtf d0, w0
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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; Test sitofp
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define double @sitofp_dx(i64 %a) nounwind ssp {
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entry:
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; CHECK: sitofp_dx
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; CHECK: scvtf d0, x0
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%conv = sitofp i64 %a to double
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ret double %conv
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}
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; Test uitofp
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define float @uitofp_sw_i1(i1 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i1
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; CHECK: and w0, w0, #0x1
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; CHECK: ucvtf s0, w0
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%conv = uitofp i1 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sw_i8(i8 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i8
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; CHECK: uxtb w0, w0
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; CHECK: ucvtf s0, w0
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%conv = uitofp i8 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sw_i16(i16 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw_i16
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; CHECK: uxth w0, w0
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; CHECK: ucvtf s0, w0
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%conv = uitofp i16 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sw(i32 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sw
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; CHECK: ucvtf s0, w0
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%conv = uitofp i32 %a to float
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ret float %conv
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}
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; Test uitofp
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define float @uitofp_sx(i64 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_sx
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; CHECK: ucvtf s0, x0
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%conv = uitofp i64 %a to float
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ret float %conv
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}
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; Test uitofp
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define double @uitofp_dw(i32 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_dw
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; CHECK: ucvtf d0, w0
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%conv = uitofp i32 %a to double
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ret double %conv
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}
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; Test uitofp
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define double @uitofp_dx(i64 %a) nounwind ssp {
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entry:
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; CHECK: uitofp_dx
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; CHECK: ucvtf d0, x0
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%conv = uitofp i64 %a to double
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ret double %conv
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}
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define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i32
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; CHECK: mov x1, x0
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%conv = trunc i64 %a to i32
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ret i32 %conv
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}
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define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i16
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
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; CHECK: uxth w0, [[REG2]]
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%conv = trunc i64 %a to i16
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ret i16 %conv
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}
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define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i8
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
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; CHECK: uxtb w0, [[REG2]]
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%conv = trunc i64 %a to i8
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ret i8 %conv
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}
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define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
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entry:
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; CHECK: i64_trunc_i1
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; CHECK: mov x[[REG:[0-9]+]], x0
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; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
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; CHECK: and w0, [[REG2]], #0x1
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%conv = trunc i64 %a to i1
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ret i1 %conv
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}
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; rdar://15101939
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define void @stack_trunc() nounwind {
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; CHECK: stack_trunc
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; CHECK: sub sp, sp, #16
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; CHECK: ldr [[REG:x[0-9]+]], [sp]
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; CHECK: mov x[[REG2:[0-9]+]], [[REG]]
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; CHECK: and [[REG3:w[0-9]+]], w[[REG2]], #0xff
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; CHECK: strb [[REG3]], [sp, #15]
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; CHECK: add sp, sp, #16
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%a = alloca i8, align 1
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%b = alloca i64, align 8
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%c = load i64* %b, align 8
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%d = trunc i64 %c to i8
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store i8 %d, i8* %a, align 1
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ret void
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}
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