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The Cost field is removed. It was only being used in a very limited way, to indicate when the scheduler should attempt to protect a live register, and it isn't really needed to do that. If we ever want the scheduler to start inserting copies in non-prohibitive situations, we'll have to rethink some things anyway. A Latency field is added. Instead of giving each node a single fixed latency, each edge can have its own latency. This will eventually be used to model various micro-architecture properties more accurately. The PointerIntPair class and an internal union are now used, which reduce the overall size. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60806 91177308-0d34-0410-b5e6-96231b3b80d8
178 lines
7.0 KiB
C++
178 lines
7.0 KiB
C++
//===---- llvm/CodeGen/ScheduleDAGSDNodes.h - SDNode Scheduling -*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ScheduleDAGSDNodes class, which implements
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// scheduling for an SDNode-based dependency graph.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_SCHEDULEDAGSDNODES_H
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#define LLVM_CODEGEN_SCHEDULEDAGSDNODES_H
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#include "llvm/CodeGen/ScheduleDAG.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/ADT/SmallSet.h"
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namespace llvm {
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/// HazardRecognizer - This determines whether or not an instruction can be
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/// issued this cycle, and whether or not a noop needs to be inserted to handle
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/// the hazard.
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class HazardRecognizer {
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public:
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virtual ~HazardRecognizer();
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enum HazardType {
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NoHazard, // This instruction can be emitted at this cycle.
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Hazard, // This instruction can't be emitted at this cycle.
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NoopHazard // This instruction can't be emitted, and needs noops.
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};
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/// getHazardType - Return the hazard type of emitting this node. There are
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/// three possible results. Either:
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/// * NoHazard: it is legal to issue this instruction on this cycle.
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/// * Hazard: issuing this instruction would stall the machine. If some
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/// other instruction is available, issue it first.
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/// * NoopHazard: issuing this instruction would break the program. If
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/// some other instruction can be issued, do so, otherwise issue a noop.
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virtual HazardType getHazardType(SDNode *) {
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return NoHazard;
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}
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/// EmitInstruction - This callback is invoked when an instruction is
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/// emitted, to advance the hazard state.
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virtual void EmitInstruction(SDNode *) {}
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/// AdvanceCycle - This callback is invoked when no instructions can be
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/// issued on this cycle without a hazard. This should increment the
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/// internal state of the hazard recognizer so that previously "Hazard"
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/// instructions will now not be hazards.
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virtual void AdvanceCycle() {}
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/// EmitNoop - This callback is invoked when a noop was added to the
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/// instruction stream.
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virtual void EmitNoop() {}
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};
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class ScheduleDAGSDNodes : public ScheduleDAG {
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public:
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SmallSet<SDNode*, 16> CommuteSet; // Nodes that should be commuted.
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ScheduleDAGSDNodes(SelectionDAG *dag, MachineBasicBlock *bb,
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const TargetMachine &tm);
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virtual ~ScheduleDAGSDNodes() {}
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/// isPassiveNode - Return true if the node is a non-scheduled leaf.
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///
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static bool isPassiveNode(SDNode *Node) {
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if (isa<ConstantSDNode>(Node)) return true;
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if (isa<ConstantFPSDNode>(Node)) return true;
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if (isa<RegisterSDNode>(Node)) return true;
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if (isa<GlobalAddressSDNode>(Node)) return true;
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if (isa<BasicBlockSDNode>(Node)) return true;
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if (isa<FrameIndexSDNode>(Node)) return true;
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if (isa<ConstantPoolSDNode>(Node)) return true;
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if (isa<JumpTableSDNode>(Node)) return true;
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if (isa<ExternalSymbolSDNode>(Node)) return true;
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if (isa<MemOperandSDNode>(Node)) return true;
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if (Node->getOpcode() == ISD::EntryToken) return true;
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return false;
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}
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/// NewSUnit - Creates a new SUnit and return a ptr to it.
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///
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SUnit *NewSUnit(SDNode *N) {
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SUnits.push_back(SUnit(N, (unsigned)SUnits.size()));
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SUnits.back().OrigNode = &SUnits.back();
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return &SUnits.back();
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}
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/// Clone - Creates a clone of the specified SUnit. It does not copy the
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/// predecessors / successors info nor the temporary scheduling states.
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///
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SUnit *Clone(SUnit *N);
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virtual SelectionDAG *getDAG() { return DAG; }
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/// BuildSchedUnits - Build SUnits from the selection dag that we are input.
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/// This SUnit graph is similar to the SelectionDAG, but represents flagged
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/// together nodes with a single SUnit.
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virtual void BuildSchedUnits();
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/// ComputeLatency - Compute node latency.
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///
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virtual void ComputeLatency(SUnit *SU);
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/// CountResults - The results of target nodes have register or immediate
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/// operands first, then an optional chain, and optional flag operands
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/// (which do not go into the machine instrs.)
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static unsigned CountResults(SDNode *Node);
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/// CountOperands - The inputs to target nodes have any actual inputs first,
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/// followed by special operands that describe memory references, then an
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/// optional chain operand, then flag operands. Compute the number of
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/// actual operands that will go into the resulting MachineInstr.
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static unsigned CountOperands(SDNode *Node);
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/// ComputeMemOperandsEnd - Find the index one past the last
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/// MemOperandSDNode operand
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static unsigned ComputeMemOperandsEnd(SDNode *Node);
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/// EmitNode - Generate machine code for an node and needed dependencies.
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/// VRBaseMap contains, for each already emitted node, the first virtual
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/// register number for the results of the node.
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///
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void EmitNode(SDNode *Node, bool IsClone,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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virtual MachineBasicBlock *EmitSchedule();
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/// Schedule - Order nodes according to selected style, filling
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/// in the Sequence member.
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///
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virtual void Schedule() = 0;
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virtual void dumpNode(const SUnit *SU) const;
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virtual std::string getGraphNodeLabel(const SUnit *SU) const;
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virtual void getCustomGraphFeatures(GraphWriter<ScheduleDAG*> &GW) const;
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private:
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/// EmitSubregNode - Generate machine code for subreg nodes.
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///
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void EmitSubregNode(SDNode *Node,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getVR - Return the virtual register corresponding to the specified result
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/// of the specified node.
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unsigned getVR(SDValue Op, DenseMap<SDValue, unsigned> &VRBaseMap);
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/// getDstOfCopyToRegUse - If the only use of the specified result number of
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/// node is a CopyToReg, return its destination register. Return 0 otherwise.
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unsigned getDstOfOnlyCopyToRegUse(SDNode *Node, unsigned ResNo) const;
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void AddOperand(MachineInstr *MI, SDValue Op, unsigned IIOpNum,
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const TargetInstrDesc *II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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/// EmitCopyFromReg - Generate machine code for an CopyFromReg node or an
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/// implicit physical register output.
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void EmitCopyFromReg(SDNode *Node, unsigned ResNo, bool IsClone,
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unsigned SrcReg,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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void CreateVirtualRegisters(SDNode *Node, MachineInstr *MI,
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const TargetInstrDesc &II,
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DenseMap<SDValue, unsigned> &VRBaseMap);
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};
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}
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#endif
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