llvm-6502/test/MC/Disassembler
Tim Northover 87773c318f AArch64: add initial NEON support
Patch by Ana Pazos.

- Completed implementation of instruction formats:
AdvSIMD three same
AdvSIMD modified immediate
AdvSIMD scalar pairwise

- Completed implementation of instruction classes
(some of the instructions in these classes
belong to yet unfinished instruction formats):
Vector Arithmetic
Vector Immediate
Vector Pairwise Arithmetic

- Initial implementation of instruction formats:
AdvSIMD scalar two-reg misc
AdvSIMD scalar three same

- Intial implementation of instruction class:
Scalar Arithmetic

- Initial clang changes to support arm v8 intrinsics.
Note: no clang changes for scalar intrinsics function name mangling yet.

- Comprehensive test cases for added instructions
To verify auto codegen, encoding, decoding, diagnosis, intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187567 91177308-0d34-0410-b5e6-96231b3b80d8
2013-08-01 09:20:35 +00:00
..
AArch64 AArch64: add initial NEON support 2013-08-01 09:20:35 +00:00
ARM Added the B9.3.19 SUBS PC, LR, #imm (Thumb2) system instruction. 2013-07-31 21:05:30 +00:00
Mips [mips] Fix FP conditional move instructions to have explicit FP condition code 2013-07-26 20:51:20 +00:00
SystemZ [SystemZ] Add RISBLG and RISBHG instruction definitions 2013-07-31 11:17:35 +00:00
X86 Changed register names (and pointer keywords) to be lower case when using Intel X86 assembler syntax. 2013-07-31 02:47:52 +00:00
XCore [XCore] Add LDAPB instructions. 2013-05-05 13:36:53 +00:00