mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
e3a85838da
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67738 91177308-0d34-0410-b5e6-96231b3b80d8
619 lines
20 KiB
C++
619 lines
20 KiB
C++
//===- MipsInstrInfo.cpp - Mips Instruction Information ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Mips implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsInstrInfo.h"
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#include "MipsTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "MipsGenInstrInfo.inc"
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using namespace llvm;
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MipsInstrInfo::MipsInstrInfo(MipsTargetMachine &tm)
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: TargetInstrInfoImpl(MipsInsts, array_lengthof(MipsInsts)),
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TM(tm), RI(*TM.getSubtargetImpl(), *this) {}
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static bool isZeroImm(const MachineOperand &op) {
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return op.isImm() && op.getImm() == 0;
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}
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/// Return true if the instruction is a register to register move and
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/// leave the source and dest operands in the passed parameters.
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bool MipsInstrInfo::
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isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, unsigned &DstReg,
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unsigned &SrcSubIdx, unsigned &DstSubIdx) const
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{
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SrcSubIdx = DstSubIdx = 0; // No sub-registers.
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// addu $dst, $src, $zero || addu $dst, $zero, $src
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// or $dst, $src, $zero || or $dst, $zero, $src
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if ((MI.getOpcode() == Mips::ADDu) || (MI.getOpcode() == Mips::OR)) {
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if (MI.getOperand(1).getReg() == Mips::ZERO) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(2).getReg();
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return true;
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} else if (MI.getOperand(2).getReg() == Mips::ZERO) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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// mov $fpDst, $fpSrc
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// mfc $gpDst, $fpSrc
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// mtc $fpDst, $gpSrc
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if (MI.getOpcode() == Mips::FMOV_S32 ||
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MI.getOpcode() == Mips::FMOV_D32 ||
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MI.getOpcode() == Mips::MFC1 ||
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MI.getOpcode() == Mips::MTC1 ) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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// addiu $dst, $src, 0
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if (MI.getOpcode() == Mips::ADDiu) {
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if ((MI.getOperand(1).isReg()) && (isZeroImm(MI.getOperand(2)))) {
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DstReg = MI.getOperand(0).getReg();
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SrcReg = MI.getOperand(1).getReg();
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return true;
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}
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}
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return false;
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}
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned MipsInstrInfo::
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isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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if ((MI->getOpcode() == Mips::LW) || (MI->getOpcode() == Mips::LWC1) ||
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(MI->getOpcode() == Mips::LDC1)) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned MipsInstrInfo::
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isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
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{
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if ((MI->getOpcode() == Mips::SW) || (MI->getOpcode() == Mips::SWC1) ||
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(MI->getOpcode() == Mips::SDC1)) {
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if ((MI->getOperand(2).isFI()) && // is a stack slot
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(MI->getOperand(1).isImm()) && // the imm is zero
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(isZeroImm(MI->getOperand(1)))) {
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FrameIndex = MI->getOperand(2).getIndex();
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return MI->getOperand(0).getReg();
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}
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}
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return 0;
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}
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/// insertNoop - If data hazard condition is found insert the target nop
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/// instruction.
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void MipsInstrInfo::
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insertNoop(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const
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{
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (MI != MBB.end()) DL = MI->getDebugLoc();
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BuildMI(MBB, MI, DL, get(Mips::NOP));
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}
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bool MipsInstrInfo::
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copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *DestRC,
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const TargetRegisterClass *SrcRC) const {
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (DestRC != SrcRC) {
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// Moves between coprocessors and cpu
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if ((DestRC == Mips::CPURegsRegisterClass) &&
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(SrcRC == Mips::FGR32RegisterClass))
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BuildMI(MBB, I, DL, get(Mips::MFC1), DestReg).addReg(SrcReg);
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else if ((DestRC == Mips::FGR32RegisterClass) &&
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(SrcRC == Mips::CPURegsRegisterClass))
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BuildMI(MBB, I, DL, get(Mips::MTC1), DestReg).addReg(SrcReg);
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// Condition registers
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else if ((SrcRC == Mips::CCRRegisterClass) &&
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(SrcReg == Mips::FCR31))
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return true; // This register is used implicitly, no copy needed.
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else if ((DestRC == Mips::CCRRegisterClass) &&
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(DestReg == Mips::FCR31))
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return true; // This register is used implicitly, no copy needed.
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// Move from/to Hi/Lo registers
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else if ((DestRC == Mips::HILORegisterClass) &&
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(SrcRC == Mips::CPURegsRegisterClass)) {
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unsigned Opc = (DestReg == Mips::HI) ? Mips::MTHI : Mips::MTLO;
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BuildMI(MBB, I, DL, get(Opc), DestReg);
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} else if ((SrcRC == Mips::HILORegisterClass) &&
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(DestRC == Mips::CPURegsRegisterClass)) {
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unsigned Opc = (SrcReg == Mips::HI) ? Mips::MFHI : Mips::MFLO;
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BuildMI(MBB, I, DL, get(Opc), DestReg);
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// Can't copy this register
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} else
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return false;
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return true;
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}
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if (DestRC == Mips::CPURegsRegisterClass)
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BuildMI(MBB, I, DL, get(Mips::ADDu), DestReg).addReg(Mips::ZERO)
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.addReg(SrcReg);
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else if (DestRC == Mips::FGR32RegisterClass)
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BuildMI(MBB, I, DL, get(Mips::FMOV_S32), DestReg).addReg(SrcReg);
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else if (DestRC == Mips::AFGR64RegisterClass)
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BuildMI(MBB, I, DL, get(Mips::FMOV_D32), DestReg).addReg(SrcReg);
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else
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// Can't copy this register
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return false;
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return true;
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}
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void MipsInstrInfo::
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storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned SrcReg, bool isKill, int FI,
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const TargetRegisterClass *RC) const {
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unsigned Opc;
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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if (RC == Mips::CPURegsRegisterClass)
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Opc = Mips::SW;
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else if (RC == Mips::FGR32RegisterClass)
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Opc = Mips::SWC1;
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else {
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assert(RC == Mips::AFGR64RegisterClass);
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Opc = Mips::SDC1;
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}
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BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill)
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.addImm(0).addFrameIndex(FI);
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}
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void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
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bool isKill, SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const
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{
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unsigned Opc;
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if (RC == Mips::CPURegsRegisterClass)
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Opc = Mips::SW;
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else if (RC == Mips::FGR32RegisterClass)
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Opc = Mips::SWC1;
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else {
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assert(RC == Mips::AFGR64RegisterClass);
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Opc = Mips::SDC1;
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}
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DebugLoc DL = DebugLoc::getUnknownLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
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.addReg(SrcReg, false, false, isKill);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i)
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MIB.addOperand(Addr[i]);
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NewMIs.push_back(MIB);
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return;
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}
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void MipsInstrInfo::
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loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
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unsigned DestReg, int FI,
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const TargetRegisterClass *RC) const
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{
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unsigned Opc;
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if (RC == Mips::CPURegsRegisterClass)
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Opc = Mips::LW;
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else if (RC == Mips::FGR32RegisterClass)
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Opc = Mips::LWC1;
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else {
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assert(RC == Mips::AFGR64RegisterClass);
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Opc = Mips::LDC1;
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}
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DebugLoc DL = DebugLoc::getUnknownLoc();
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if (I != MBB.end()) DL = I->getDebugLoc();
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BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
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}
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void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const {
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unsigned Opc;
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if (RC == Mips::CPURegsRegisterClass)
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Opc = Mips::LW;
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else if (RC == Mips::FGR32RegisterClass)
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Opc = Mips::LWC1;
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else {
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assert(RC == Mips::AFGR64RegisterClass);
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Opc = Mips::LDC1;
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}
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DebugLoc DL = DebugLoc::getUnknownLoc();
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MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
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for (unsigned i = 0, e = Addr.size(); i != e; ++i)
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MIB.addOperand(Addr[i]);
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NewMIs.push_back(MIB);
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return;
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}
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MachineInstr *MipsInstrInfo::
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foldMemoryOperandImpl(MachineFunction &MF,
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MachineInstr* MI,
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const SmallVectorImpl<unsigned> &Ops, int FI) const
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{
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if (Ops.size() != 1) return NULL;
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MachineInstr *NewMI = NULL;
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switch (MI->getOpcode()) {
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case Mips::ADDu:
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if ((MI->getOperand(0).isReg()) &&
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(MI->getOperand(1).isReg()) &&
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(MI->getOperand(1).getReg() == Mips::ZERO) &&
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(MI->getOperand(2).isReg())) {
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if (Ops[0] == 0) { // COPY -> STORE
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unsigned SrcReg = MI->getOperand(2).getReg();
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bool isKill = MI->getOperand(2).isKill();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::SW))
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.addReg(SrcReg, false, false, isKill)
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.addImm(0).addFrameIndex(FI);
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} else { // COPY -> LOAD
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unsigned DstReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(Mips::LW))
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.addReg(DstReg, true, false, false, isDead)
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.addImm(0).addFrameIndex(FI);
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}
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}
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break;
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case Mips::FMOV_S32:
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case Mips::FMOV_D32:
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if ((MI->getOperand(0).isReg()) &&
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(MI->getOperand(1).isReg())) {
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const TargetRegisterClass
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*RC = RI.getRegClass(MI->getOperand(0).getReg());
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unsigned StoreOpc, LoadOpc;
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if (RC == Mips::FGR32RegisterClass) {
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LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
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} else {
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assert(RC == Mips::AFGR64RegisterClass);
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LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
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}
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if (Ops[0] == 0) { // COPY -> STORE
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unsigned SrcReg = MI->getOperand(1).getReg();
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bool isKill = MI->getOperand(1).isKill();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(StoreOpc))
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.addReg(SrcReg, false, false, isKill)
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.addImm(0).addFrameIndex(FI) ;
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} else { // COPY -> LOAD
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unsigned DstReg = MI->getOperand(0).getReg();
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bool isDead = MI->getOperand(0).isDead();
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NewMI = BuildMI(MF, MI->getDebugLoc(), get(LoadOpc))
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.addReg(DstReg, true, false, false, isDead)
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.addImm(0).addFrameIndex(FI);
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}
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}
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break;
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}
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return NewMI;
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}
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//===----------------------------------------------------------------------===//
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// Branch Analysis
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//===----------------------------------------------------------------------===//
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/// GetCondFromBranchOpc - Return the Mips CC that matches
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/// the correspondent Branch instruction opcode.
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static Mips::CondCode GetCondFromBranchOpc(unsigned BrOpc)
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{
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switch (BrOpc) {
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default: return Mips::COND_INVALID;
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case Mips::BEQ : return Mips::COND_E;
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case Mips::BNE : return Mips::COND_NE;
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case Mips::BGTZ : return Mips::COND_GZ;
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case Mips::BGEZ : return Mips::COND_GEZ;
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case Mips::BLTZ : return Mips::COND_LZ;
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case Mips::BLEZ : return Mips::COND_LEZ;
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// We dont do fp branch analysis yet!
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case Mips::BC1T :
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case Mips::BC1F : return Mips::COND_INVALID;
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}
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}
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/// GetCondBranchFromCond - Return the Branch instruction
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/// opcode that matches the cc.
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unsigned Mips::GetCondBranchFromCond(Mips::CondCode CC)
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{
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case Mips::COND_E : return Mips::BEQ;
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case Mips::COND_NE : return Mips::BNE;
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case Mips::COND_GZ : return Mips::BGTZ;
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case Mips::COND_GEZ : return Mips::BGEZ;
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case Mips::COND_LZ : return Mips::BLTZ;
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case Mips::COND_LEZ : return Mips::BLEZ;
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case Mips::FCOND_F:
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case Mips::FCOND_UN:
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case Mips::FCOND_EQ:
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case Mips::FCOND_UEQ:
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case Mips::FCOND_OLT:
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case Mips::FCOND_ULT:
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case Mips::FCOND_OLE:
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case Mips::FCOND_ULE:
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case Mips::FCOND_SF:
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case Mips::FCOND_NGLE:
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case Mips::FCOND_SEQ:
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case Mips::FCOND_NGL:
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case Mips::FCOND_LT:
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case Mips::FCOND_NGE:
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case Mips::FCOND_LE:
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case Mips::FCOND_NGT: return Mips::BC1T;
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case Mips::FCOND_T:
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case Mips::FCOND_OR:
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case Mips::FCOND_NEQ:
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case Mips::FCOND_OGL:
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case Mips::FCOND_UGE:
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case Mips::FCOND_OGE:
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case Mips::FCOND_UGT:
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case Mips::FCOND_OGT:
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case Mips::FCOND_ST:
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case Mips::FCOND_GLE:
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case Mips::FCOND_SNE:
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case Mips::FCOND_GL:
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case Mips::FCOND_NLT:
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case Mips::FCOND_GE:
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case Mips::FCOND_NLE:
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case Mips::FCOND_GT: return Mips::BC1F;
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}
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}
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/// GetOppositeBranchCondition - Return the inverse of the specified
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/// condition, e.g. turning COND_E to COND_NE.
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Mips::CondCode Mips::GetOppositeBranchCondition(Mips::CondCode CC)
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{
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switch (CC) {
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default: assert(0 && "Illegal condition code!");
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case Mips::COND_E : return Mips::COND_NE;
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case Mips::COND_NE : return Mips::COND_E;
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case Mips::COND_GZ : return Mips::COND_LEZ;
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case Mips::COND_GEZ : return Mips::COND_LZ;
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case Mips::COND_LZ : return Mips::COND_GEZ;
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case Mips::COND_LEZ : return Mips::COND_GZ;
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case Mips::FCOND_F : return Mips::FCOND_T;
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case Mips::FCOND_UN : return Mips::FCOND_OR;
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case Mips::FCOND_EQ : return Mips::FCOND_NEQ;
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case Mips::FCOND_UEQ: return Mips::FCOND_OGL;
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case Mips::FCOND_OLT: return Mips::FCOND_UGE;
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case Mips::FCOND_ULT: return Mips::FCOND_OGE;
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case Mips::FCOND_OLE: return Mips::FCOND_UGT;
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case Mips::FCOND_ULE: return Mips::FCOND_OGT;
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case Mips::FCOND_SF: return Mips::FCOND_ST;
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case Mips::FCOND_NGLE:return Mips::FCOND_GLE;
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case Mips::FCOND_SEQ: return Mips::FCOND_SNE;
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case Mips::FCOND_NGL: return Mips::FCOND_GL;
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case Mips::FCOND_LT: return Mips::FCOND_NLT;
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case Mips::FCOND_NGE: return Mips::FCOND_GE;
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case Mips::FCOND_LE: return Mips::FCOND_NLE;
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case Mips::FCOND_NGT: return Mips::FCOND_GT;
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}
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}
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bool MipsInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
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MachineBasicBlock *&TBB,
|
|
MachineBasicBlock *&FBB,
|
|
SmallVectorImpl<MachineOperand> &Cond,
|
|
bool AllowModify) const
|
|
{
|
|
// If the block has no terminators, it just falls into the block after it.
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
|
|
return false;
|
|
|
|
// Get the last instruction in the block.
|
|
MachineInstr *LastInst = I;
|
|
|
|
// If there is only one terminator instruction, process it.
|
|
unsigned LastOpc = LastInst->getOpcode();
|
|
if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
|
|
if (!LastInst->getDesc().isBranch())
|
|
return true;
|
|
|
|
// Unconditional branch
|
|
if (LastOpc == Mips::J) {
|
|
TBB = LastInst->getOperand(0).getMBB();
|
|
return false;
|
|
}
|
|
|
|
Mips::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode());
|
|
if (BranchCode == Mips::COND_INVALID)
|
|
return true; // Can't handle indirect branch.
|
|
|
|
// Conditional branch
|
|
// Block ends with fall-through condbranch.
|
|
if (LastOpc != Mips::COND_INVALID) {
|
|
int LastNumOp = LastInst->getNumOperands();
|
|
|
|
TBB = LastInst->getOperand(LastNumOp-1).getMBB();
|
|
Cond.push_back(MachineOperand::CreateImm(BranchCode));
|
|
|
|
for (int i=0; i<LastNumOp-1; i++) {
|
|
Cond.push_back(LastInst->getOperand(i));
|
|
}
|
|
|
|
return false;
|
|
}
|
|
}
|
|
|
|
// Get the instruction before it if it is a terminator.
|
|
MachineInstr *SecondLastInst = I;
|
|
|
|
// If there are three terminators, we don't know what sort of block this is.
|
|
if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
|
|
return true;
|
|
|
|
// If the block ends with Mips::J and a Mips::BNE/Mips::BEQ, handle it.
|
|
unsigned SecondLastOpc = SecondLastInst->getOpcode();
|
|
Mips::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc);
|
|
|
|
if (BranchCode != Mips::COND_INVALID && LastOpc == Mips::J) {
|
|
int SecondNumOp = SecondLastInst->getNumOperands();
|
|
|
|
TBB = SecondLastInst->getOperand(SecondNumOp-1).getMBB();
|
|
Cond.push_back(MachineOperand::CreateImm(BranchCode));
|
|
|
|
for (int i=0; i<SecondNumOp-1; i++) {
|
|
Cond.push_back(SecondLastInst->getOperand(i));
|
|
}
|
|
|
|
FBB = LastInst->getOperand(0).getMBB();
|
|
return false;
|
|
}
|
|
|
|
// If the block ends with two unconditional branches, handle it. The last
|
|
// one is not executed, so remove it.
|
|
if ((SecondLastOpc == Mips::J) && (LastOpc == Mips::J)) {
|
|
TBB = SecondLastInst->getOperand(0).getMBB();
|
|
I = LastInst;
|
|
if (AllowModify)
|
|
I->eraseFromParent();
|
|
return false;
|
|
}
|
|
|
|
// Otherwise, can't handle this.
|
|
return true;
|
|
}
|
|
|
|
unsigned MipsInstrInfo::
|
|
InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
|
|
MachineBasicBlock *FBB,
|
|
const SmallVectorImpl<MachineOperand> &Cond) const {
|
|
// FIXME this should probably have a DebugLoc argument
|
|
DebugLoc dl = DebugLoc::getUnknownLoc();
|
|
// Shouldn't be a fall through.
|
|
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
|
|
assert((Cond.size() == 3 || Cond.size() == 2 || Cond.size() == 0) &&
|
|
"Mips branch conditions can have two|three components!");
|
|
|
|
if (FBB == 0) { // One way branch.
|
|
if (Cond.empty()) {
|
|
// Unconditional branch?
|
|
BuildMI(&MBB, dl, get(Mips::J)).addMBB(TBB);
|
|
} else {
|
|
// Conditional branch.
|
|
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
|
|
const TargetInstrDesc &TID = get(Opc);
|
|
|
|
if (TID.getNumOperands() == 3)
|
|
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
|
|
.addReg(Cond[2].getReg())
|
|
.addMBB(TBB);
|
|
else
|
|
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg())
|
|
.addMBB(TBB);
|
|
|
|
}
|
|
return 1;
|
|
}
|
|
|
|
// Two-way Conditional branch.
|
|
unsigned Opc = GetCondBranchFromCond((Mips::CondCode)Cond[0].getImm());
|
|
const TargetInstrDesc &TID = get(Opc);
|
|
|
|
if (TID.getNumOperands() == 3)
|
|
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addReg(Cond[2].getReg())
|
|
.addMBB(TBB);
|
|
else
|
|
BuildMI(&MBB, dl, TID).addReg(Cond[1].getReg()).addMBB(TBB);
|
|
|
|
BuildMI(&MBB, dl, get(Mips::J)).addMBB(FBB);
|
|
return 2;
|
|
}
|
|
|
|
unsigned MipsInstrInfo::
|
|
RemoveBranch(MachineBasicBlock &MBB) const
|
|
{
|
|
MachineBasicBlock::iterator I = MBB.end();
|
|
if (I == MBB.begin()) return 0;
|
|
--I;
|
|
if (I->getOpcode() != Mips::J &&
|
|
GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
|
|
return 0;
|
|
|
|
// Remove the branch.
|
|
I->eraseFromParent();
|
|
|
|
I = MBB.end();
|
|
|
|
if (I == MBB.begin()) return 1;
|
|
--I;
|
|
if (GetCondFromBranchOpc(I->getOpcode()) == Mips::COND_INVALID)
|
|
return 1;
|
|
|
|
// Remove the branch.
|
|
I->eraseFromParent();
|
|
return 2;
|
|
}
|
|
|
|
/// BlockHasNoFallThrough - Analyze if MachineBasicBlock does not
|
|
/// fall-through into its successor block.
|
|
bool MipsInstrInfo::
|
|
BlockHasNoFallThrough(const MachineBasicBlock &MBB) const
|
|
{
|
|
if (MBB.empty()) return false;
|
|
|
|
switch (MBB.back().getOpcode()) {
|
|
case Mips::RET: // Return.
|
|
case Mips::JR: // Indirect branch.
|
|
case Mips::J: // Uncond branch.
|
|
return true;
|
|
default: return false;
|
|
}
|
|
}
|
|
|
|
/// ReverseBranchCondition - Return the inverse opcode of the
|
|
/// specified Branch instruction.
|
|
bool MipsInstrInfo::
|
|
ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
|
|
{
|
|
assert( (Cond.size() == 3 || Cond.size() == 2) &&
|
|
"Invalid Mips branch condition!");
|
|
Cond[0].setImm(GetOppositeBranchCondition((Mips::CondCode)Cond[0].getImm()));
|
|
return false;
|
|
}
|