Ulrich Weigand 878c6281d3 [SystemZ] Add CodeGen support for v4f32 ... The architecture doesn't really have any native v4f32 operations except v4f32->v2f64 and v2f64->v4f32 conversions, with only half of the v4f32 elements being used. Even so, using vector registers for <4 x float> and scalarising individual operations is much better than generating completely scalar code, since there's much less register pressure. It's also more efficient to do v4f32 comparisons by extending to 2 v2f64s, comparing those, then packing the result. This particularly helps with llvmpipe. Based on a patch by Richard Sandiford. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236523 91177308-0d34-0410-b5e6-96231b3b80d8		2015-05-05 19:27:45 +00:00
..
AArch64	[ShrinkWrap] Add (a simplified version) of shrink-wrapping.	2015-05-05 17:38:16 +00:00
ARM	Revert "Fix IfConverter to handle regmask machine operands."	2015-05-05 18:49:05 +00:00
BPF
CPP
Generic	[Hexagon] r236351 fix does not work on builder configurations yet.	2015-05-01 22:39:20 +00:00
Hexagon
Inputs
Mips	[mips] Generate code for insert/extract operations when using the N64 ABI and MSA.	2015-05-05 10:32:24 +00:00
MSP430
NVPTX
PowerPC	This patch adds ABI support for v1i128 data type.	2015-05-05 16:10:44 +00:00
R600	R600/SI: Add VCC as an implict def of SI_KILL	2015-05-01 03:44:09 +00:00
SPARC
SystemZ	[SystemZ] Add CodeGen support for v4f32	2015-05-05 19:27:45 +00:00
Thumb
Thumb2
WinEH	Flip r236172 testcase RUN option ordering for BSD sed(1). NFC.	2015-04-30 00:07:34 +00:00
X86	Re-land "[WinEH] Add an EH registration and state insertion pass for 32-bit x86"	2015-05-05 17:44:16 +00:00
XCore