llvm-6502/lib/Target/CellSPU
Jakob Stoklund Olesen 600f171486 RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@108099 91177308-0d34-0410-b5e6-96231b3b80d8
2010-07-11 19:19:13 +00:00
..
AsmPrinter fix some inconsistent line endings, patch by Jakub Staszak! 2010-05-01 17:36:49 +00:00
TargetInfo
CellSDKIntrinsics.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
CMakeLists.txt Add skeleton target-specific SelectionDAGInfo files. 2010-04-16 23:04:22 +00:00
Makefile
README.txt Testing svn access with a note added to documentation. 2010-05-07 18:06:28 +00:00
SPU64InstrInfo.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
SPU128InstrInfo.td
SPU.h Remove a bunch of integer width predicate functions in favor of MathExtras. 2010-03-29 19:07:58 +00:00
SPU.td
SPUCallingConv.td Switch SPU calling convention (function arguments) 2010-07-08 21:15:22 +00:00
SPUFrameInfo.cpp
SPUFrameInfo.h Remove some unused/redundant code. 2010-07-05 18:40:09 +00:00
SPUHazardRecognizers.cpp
SPUHazardRecognizers.h
SPUInstrBuilder.h
SPUInstrFormats.td
SPUInstrInfo.cpp RISC architectures get their memory operand folding for free. 2010-07-11 19:19:13 +00:00
SPUInstrInfo.h RISC architectures get their memory operand folding for free. 2010-07-11 19:19:13 +00:00
SPUInstrInfo.td Fix encoding of 'sf' and 'sfh' instructions. 2010-05-10 08:13:49 +00:00
SPUISelDAGToDAG.cpp Remove initialized but otherwise unused variables. 2010-06-29 11:22:26 +00:00
SPUISelLowering.cpp Switch SPU calling convention (function arguments) 2010-07-08 21:15:22 +00:00
SPUISelLowering.h Split the SDValue out of OutputArg so that SelectionDAG-independent 2010-07-07 15:54:55 +00:00
SPUMachineFunction.h Move per-function state out of TargetLowering subclasses and into 2010-04-17 14:41:14 +00:00
SPUMathInstr.td disambiguate some types, add a fixme about some 2010-03-08 18:59:49 +00:00
SPUMCAsmInfo.cpp "On SPU, variables in the .bss section that are allocated with the .lcomm directive are not aligned on 16 byte boundaries. This causes misaligned loads, as the generated assembly assumes this "default" alignment. 2010-04-09 18:27:03 +00:00
SPUMCAsmInfo.h
SPUNodes.td Flag SPU's function call sequence together. 2010-06-08 07:55:16 +00:00
SPUOperands.td do some serious surgery on CellSPU to get it back into a world 2010-03-15 05:53:47 +00:00
SPURegisterInfo.cpp Switch SPU calling convention (function arguments) 2010-07-08 21:15:22 +00:00
SPURegisterInfo.h Switch SPU calling convention (function arguments) 2010-07-08 21:15:22 +00:00
SPURegisterInfo.td
SPURegisterNames.h
SPUSchedule.td Make processor FUs unique for given itinerary. This extends the limit of 32 2010-04-18 20:31:01 +00:00
SPUSelectionDAGInfo.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSelectionDAGInfo.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUSubtarget.cpp
SPUSubtarget.h
SPUTargetMachine.cpp Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00
SPUTargetMachine.h Implement a bunch more TargetSelectionDAGInfo infrastructure. 2010-05-11 17:31:57 +00:00

//===- README.txt - Notes for improving CellSPU-specific code gen ---------===//

This code was contributed by a team from the Computer Systems Research
Department in The Aerospace Corporation:

- Scott Michel (head bottle washer and much of the non-floating point
  instructions)
- Mark Thomas (floating point instructions)
- Michael AuYeung (intrinsics)
- Chandler Carruth (LLVM expertise)
- Nehal Desai (debugging, i32 operations, RoadRunner SPU expertise)

Some minor fixes added by Kalle Raiskila.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, NONINFRINGEMENT, OR
OTHERWISE.  IN NO EVENT SHALL THE AEROSPACE CORPORATION BE LIABLE FOR DAMAGES
OF ANY KIND OR NATURE WHETHER BASED IN CONTRACT, TORT, OR OTHERWISE ARISING
OUT OF OR IN CONNECTION WITH THE USE OF THE SOFTWARE INCLUDING, WITHOUT
LIMITATION, DAMAGES RESULTING FROM LOST OR CONTAMINATED DATA, LOST PROFITS OR
REVENUE, COMPUTER MALFUNCTION, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL,
OR PUNITIVE  DAMAGES, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES OR
SUCH DAMAGES ARE FORESEEABLE.

---------------------------------------------------------------------------
--WARNING--:
--WARNING--: The CellSPU work is work-in-progress and "alpha" quality code.
--WARNING--:

If you are brave enough to try this code or help to hack on it, be sure
to add 'spu' to configure's --enable-targets option, e.g.:

        ./configure <your_configure_flags_here> \
           --enable-targets=x86,x86_64,powerpc,spu

---------------------------------------------------------------------------

TODO:
* Create a machine pass for performing dual-pipeline scheduling specifically
  for CellSPU, and insert branch prediction instructions as needed.

* i32 instructions:

  * i32 division (work-in-progress)

* i64 support (see i64operations.c test harness):

  * shifts and comparison operators: done
  * sign and zero extension: done
  * addition: done
  * subtraction: needed
  * multiplication: done

* i128 support:

  * zero extension, any extension: done
  * sign extension: needed
  * arithmetic operators (add, sub, mul, div): needed
  * logical operations (and, or, shl, srl, sra, xor, nor, nand): needed

    * or: done

* f64 support

  * Comparison operators:
    SETOEQ              unimplemented
    SETOGT              unimplemented
    SETOGE              unimplemented
    SETOLT              unimplemented
    SETOLE              unimplemented
    SETONE              unimplemented
    SETO                done (lowered)
    SETUO               done (lowered)
    SETUEQ              unimplemented
    SETUGT              unimplemented
    SETUGE              unimplemented
    SETULT              unimplemented
    SETULE              unimplemented
    SETUNE              unimplemented

* LLVM vector suport

  * VSETCC needs to be implemented. It's pretty straightforward to code, but
    needs implementation.

* Intrinsics

  * spu.h instrinsics added but not tested. Need to have an operational
    llvm-spu-gcc in order to write a unit test harness.

===-------------------------------------------------------------------------===