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https://github.com/c64scene-ar/llvm-6502.git
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d410eaba04
test suite failures. The failures occur at each stage, and only get worse, so I'm reverting all of them. Please resubmit these patches, one at a time, after verifying that the regression test suite passes. Never submit a patch without running the regression test suite. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155372 91177308-0d34-0410-b5e6-96231b3b80d8
135 lines
5.2 KiB
TableGen
135 lines
5.2 KiB
TableGen
//=- HexagonInstrInfoV3.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the Hexagon V3 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// J +
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//===----------------------------------------------------------------------===//
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// Call subroutine.
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let isCall = 1, neverHasSideEffects = 1,
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Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
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P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
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def CALLv3 : JInst<(outs), (ins calltarget:$dst, variable_ops),
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"call $dst", []>, Requires<[HasV3T]>;
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}
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//===----------------------------------------------------------------------===//
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// J -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// JR +
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//===----------------------------------------------------------------------===//
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// Call subroutine from register.
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let isCall = 1, neverHasSideEffects = 1,
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Defs = [D0, D1, D2, D3, D4, D5, D6, D7, R28, R31,
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P0, P1, P2, P3, LC0, LC1, SA0, SA1] in {
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def CALLRv3 : JRInst<(outs), (ins IntRegs:$dst, variable_ops),
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"callr $dst",
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[]>, Requires<[HasV3TOnly]>;
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}
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// if(p?.new) jumpr:t r?
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let isReturn = 1, isTerminator = 1, isBarrier = 1,
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Defs = [PC], Uses = [R31] in {
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def JMPR_cPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) jumpr:t $src2",
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[]>, Requires<[HasV3T]>;
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}
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// if (!p?.new) jumpr:t r?
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let isReturn = 1, isTerminator = 1, isBarrier = 1,
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Defs = [PC], Uses = [R31] in {
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def JMPR_cNotPnewt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) jumpr:t $src2",
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[]>, Requires<[HasV3T]>;
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}
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// Not taken.
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// if(p?.new) jumpr:nt r?
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let isReturn = 1, isTerminator = 1, isBarrier = 1,
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Defs = [PC], Uses = [R31] in {
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def JMPR_cPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
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"if ($src1.new) jumpr:nt $src2",
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[]>, Requires<[HasV3T]>;
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}
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// if (!p?.new) jumpr:nt r?
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let isReturn = 1, isTerminator = 1, isBarrier = 1,
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Defs = [PC], Uses = [R31] in {
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def JMPR_cNotPnewNt: JRInst<(outs), (ins PredRegs:$src1, IntRegs:$src2),
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"if (!$src1.new) jumpr:nt $src2",
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[]>, Requires<[HasV3T]>;
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}
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//===----------------------------------------------------------------------===//
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// JR -
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// ALU64/ALU +
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//===----------------------------------------------------------------------===//
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let AddedComplexity = 200 in
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def MAXw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = max($src2, $src1)",
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[(set DoubleRegs:$dst, (select (i1 (setlt DoubleRegs:$src2,
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DoubleRegs:$src1)),
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DoubleRegs:$src1,
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DoubleRegs:$src2))]>,
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Requires<[HasV3T]>;
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let AddedComplexity = 200 in
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def MINw_dd : ALU64_rr<(outs DoubleRegs:$dst), (ins DoubleRegs:$src1,
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DoubleRegs:$src2),
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"$dst = min($src2, $src1)",
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[(set DoubleRegs:$dst, (select (i1 (setgt DoubleRegs:$src2,
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DoubleRegs:$src1)),
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DoubleRegs:$src1,
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DoubleRegs:$src2))]>,
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Requires<[HasV3T]>;
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//===----------------------------------------------------------------------===//
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// ALU64/ALU -
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//===----------------------------------------------------------------------===//
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//def : Pat <(brcond (i1 (seteq IntRegs:$src1, 0)), bb:$offset),
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// (JMP_RegEzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setne IntRegs:$src1, 0)), bb:$offset),
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// (JMP_RegNzt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setle IntRegs:$src1, 0)), bb:$offset),
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// (JMP_RegLezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setge IntRegs:$src1, 0)), bb:$offset),
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// (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
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//def : Pat <(brcond (i1 (setgt IntRegs:$src1, -1)), bb:$offset),
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// (JMP_RegGezt IntRegs:$src1, bb:$offset)>, Requires<[HasV3T]>;
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// Map call instruction
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def : Pat<(call IntRegs:$dst),
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(CALLRv3 IntRegs:$dst)>, Requires<[HasV3T]>;
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def : Pat<(call tglobaladdr:$dst),
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(CALLv3 tglobaladdr:$dst)>, Requires<[HasV3T]>;
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def : Pat<(call texternalsym:$dst),
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(CALLv3 texternalsym:$dst)>, Requires<[HasV3T]>;
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