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its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181041 91177308-0d34-0410-b5e6-96231b3b80d8
449 lines
15 KiB
C++
449 lines
15 KiB
C++
//===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsDAGToDAGISel specialized for mips32/64.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-isel"
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#include "MipsSEISelDAGToDAG.h"
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#include "Mips.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "MipsAnalyzeImmediate.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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if (Subtarget.inMips16Mode())
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return false;
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return MipsDAGToDAGISel::runOnMachineFunction(MF);
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}
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void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
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MachineFunction &MF) {
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MachineInstrBuilder MIB(MF, &MI);
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unsigned Mask = MI.getOperand(1).getImm();
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unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
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if (Mask & 1)
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MIB.addReg(Mips::DSPPos, Flag);
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if (Mask & 2)
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MIB.addReg(Mips::DSPSCount, Flag);
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if (Mask & 4)
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MIB.addReg(Mips::DSPCarry, Flag);
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if (Mask & 8)
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MIB.addReg(Mips::DSPOutFlag, Flag);
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if (Mask & 16)
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MIB.addReg(Mips::DSPCCond, Flag);
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if (Mask & 32)
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MIB.addReg(Mips::DSPEFI, Flag);
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}
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bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
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const MachineInstr& MI) {
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unsigned DstReg = 0, ZeroReg = 0;
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// Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
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if ((MI.getOpcode() == Mips::ADDiu) &&
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(MI.getOperand(1).getReg() == Mips::ZERO) &&
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(MI.getOperand(2).getImm() == 0)) {
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DstReg = MI.getOperand(0).getReg();
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ZeroReg = Mips::ZERO;
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} else if ((MI.getOpcode() == Mips::DADDiu) &&
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(MI.getOperand(1).getReg() == Mips::ZERO_64) &&
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(MI.getOperand(2).getImm() == 0)) {
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DstReg = MI.getOperand(0).getReg();
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ZeroReg = Mips::ZERO_64;
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}
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if (!DstReg)
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return false;
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// Replace uses with ZeroReg.
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for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
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E = MRI->use_end(); U != E;) {
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MachineOperand &MO = U.getOperand();
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unsigned OpNo = U.getOperandNo();
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MachineInstr *MI = MO.getParent();
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++U;
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// Do not replace if it is a phi's operand or is tied to def operand.
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if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
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continue;
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MO.setReg(ZeroReg);
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}
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return true;
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}
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void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
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MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
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if (!MipsFI->globalBaseRegSet())
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return;
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MachineBasicBlock &MBB = MF.front();
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MachineBasicBlock::iterator I = MBB.begin();
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MachineRegisterInfo &RegInfo = MF.getRegInfo();
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
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unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
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const TargetRegisterClass *RC;
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if (Subtarget.isABI_N64())
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RC = (const TargetRegisterClass*)&Mips::CPU64RegsRegClass;
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else
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RC = (const TargetRegisterClass*)&Mips::CPURegsRegClass;
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V0 = RegInfo.createVirtualRegister(RC);
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V1 = RegInfo.createVirtualRegister(RC);
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if (Subtarget.isABI_N64()) {
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MF.getRegInfo().addLiveIn(Mips::T9_64);
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MBB.addLiveIn(Mips::T9_64);
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// daddu $v1, $v0, $t9
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// daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
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.addReg(Mips::T9_64);
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BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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return;
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}
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if (MF.getTarget().getRelocationModel() == Reloc::Static) {
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// Set global register to __gnu_local_gp.
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//
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// lui $v0, %hi(__gnu_local_gp)
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// addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
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.addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
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return;
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}
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MF.getRegInfo().addLiveIn(Mips::T9);
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MBB.addLiveIn(Mips::T9);
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if (Subtarget.isABI_N32()) {
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// lui $v0, %hi(%neg(%gp_rel(fname)))
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// addu $v1, $v0, $t9
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// addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
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const GlobalValue *FName = MF.getFunction();
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BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
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.addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
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return;
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}
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assert(Subtarget.isABI_O32());
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// For O32 ABI, the following instruction sequence is emitted to initialize
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// the global base register:
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//
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// 0. lui $2, %hi(_gp_disp)
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// 1. addiu $2, $2, %lo(_gp_disp)
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// 2. addu $globalbasereg, $2, $t9
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//
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// We emit only the last instruction here.
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//
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// GNU linker requires that the first two instructions appear at the beginning
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// of a function and no instructions be inserted before or between them.
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// The two instructions are emitted during lowering to MC layer in order to
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// avoid any reordering.
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//
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// Register $2 (Mips::V0) is added to the list of live-in registers to ensure
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// the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
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// reads it.
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MF.getRegInfo().addLiveIn(Mips::V0);
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MBB.addLiveIn(Mips::V0);
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BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
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.addReg(Mips::V0).addReg(Mips::T9);
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}
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void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
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initGlobalBaseReg(MF);
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MachineRegisterInfo *MRI = &MF.getRegInfo();
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for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
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++MFI)
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for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
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if (I->getOpcode() == Mips::RDDSP)
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addDSPCtrlRegOperands(false, *I, MF);
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else if (I->getOpcode() == Mips::WRDSP)
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addDSPCtrlRegOperands(true, *I, MF);
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else
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replaceUsesWithZeroReg(MRI, *I);
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}
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}
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SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
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SDValue CmpLHS, DebugLoc DL,
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SDNode *Node) const {
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unsigned Opc = InFlag.getOpcode(); (void)Opc;
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assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
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(Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
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"(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
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SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
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SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
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EVT VT = LHS.getValueType();
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SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
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SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
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SDValue(Carry, 0), RHS);
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return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
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SDValue(AddCarry, 0));
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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EVT ValTy = Addr.getValueType();
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// if Address is FI, get the TargetFrameIndex.
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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Offset = CurDAG->getTargetConstant(0, ValTy);
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return true;
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}
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// on PIC code Load GA
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if (Addr.getOpcode() == MipsISD::Wrapper) {
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Base = Addr.getOperand(0);
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Offset = Addr.getOperand(1);
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return true;
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}
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if (TM.getRelocationModel() != Reloc::PIC_) {
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if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
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Addr.getOpcode() == ISD::TargetGlobalAddress))
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return false;
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}
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// Addresses of the form FI+const or FI|const
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
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if (isInt<16>(CN->getSExtValue())) {
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// If the first operand is a FI, get the TargetFI Node
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if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
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(Addr.getOperand(0)))
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Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
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else
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Base = Addr.getOperand(0);
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Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
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return true;
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}
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}
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// Operand is a result from an ADD.
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if (Addr.getOpcode() == ISD::ADD) {
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// When loading from constant pools, load the lower address part in
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// the instruction itself. Example, instead of:
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// lui $2, %hi($CPI1_0)
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// addiu $2, $2, %lo($CPI1_0)
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// lwc1 $f0, 0($2)
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// Generate:
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// lui $2, %hi($CPI1_0)
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// lwc1 $f0, %lo($CPI1_0)($2)
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if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
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Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
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SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
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if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
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isa<JumpTableSDNode>(Opnd0)) {
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Base = Addr.getOperand(0);
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Offset = Opnd0;
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return true;
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}
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}
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}
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return false;
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}
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bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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Base = Addr;
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Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
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return true;
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}
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bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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return selectAddrRegImm(Addr, Base, Offset) ||
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selectAddrDefault(Addr, Base, Offset);
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}
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std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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DebugLoc DL = Node->getDebugLoc();
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///
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// Instruction Selection not handled by the auto-generated
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// tablegen selection should be handled here.
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///
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SDNode *Result;
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switch(Opcode) {
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default: break;
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case ISD::SUBE: {
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SDValue InFlag = Node->getOperand(2);
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Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
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return std::make_pair(true, Result);
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}
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case ISD::ADDE: {
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if (Subtarget.hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
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break;
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SDValue InFlag = Node->getOperand(2);
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Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
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return std::make_pair(true, Result);
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}
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case ISD::ConstantFP: {
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ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
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if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
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if (Subtarget.hasMips64()) {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
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Mips::ZERO_64, MVT::i64);
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Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
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} else {
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SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
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Mips::ZERO, MVT::i32);
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Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
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Zero);
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}
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return std::make_pair(true, Result);
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}
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break;
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}
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case ISD::Constant: {
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const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
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unsigned Size = CN->getValueSizeInBits(0);
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if (Size == 32)
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break;
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MipsAnalyzeImmediate AnalyzeImm;
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int64_t Imm = CN->getSExtValue();
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const MipsAnalyzeImmediate::InstSeq &Seq =
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AnalyzeImm.Analyze(Imm, Size, false);
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MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
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DebugLoc DL = CN->getDebugLoc();
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SDNode *RegOpnd;
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SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
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MVT::i64);
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// The first instruction can be a LUi which is different from other
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// instructions (ADDiu, ORI and SLL) in that it does not have a register
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// operand.
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if (Inst->Opc == Mips::LUi64)
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RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
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else
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RegOpnd =
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CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
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CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
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ImmOpnd);
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// The remaining instructions in the sequence are handled here.
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for (++Inst; Inst != Seq.end(); ++Inst) {
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ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
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MVT::i64);
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RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
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SDValue(RegOpnd, 0), ImmOpnd);
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}
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return std::make_pair(true, RegOpnd);
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}
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case MipsISD::ThreadPointer: {
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EVT PtrVT = TLI.getPointerTy();
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unsigned RdhwrOpc, SrcReg, DestReg;
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if (PtrVT == MVT::i32) {
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RdhwrOpc = Mips::RDHWR;
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SrcReg = Mips::HWR29;
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DestReg = Mips::V1;
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} else {
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RdhwrOpc = Mips::RDHWR64;
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SrcReg = Mips::HWR29_64;
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DestReg = Mips::V1_64;
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}
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SDNode *Rdhwr =
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CurDAG->getMachineNode(RdhwrOpc, Node->getDebugLoc(),
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Node->getValueType(0),
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CurDAG->getRegister(SrcReg, PtrVT));
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SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
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SDValue(Rdhwr, 0));
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SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
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ReplaceUses(SDValue(Node, 0), ResNode);
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return std::make_pair(true, ResNode.getNode());
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}
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case MipsISD::InsertLOHI: {
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unsigned RCID = Subtarget.hasDSP() ? Mips::ACRegsDSPRegClassID :
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Mips::ACRegsRegClassID;
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SDValue RegClass = CurDAG->getTargetConstant(RCID, MVT::i32);
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SDValue LoIdx = CurDAG->getTargetConstant(Mips::sub_lo, MVT::i32);
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SDValue HiIdx = CurDAG->getTargetConstant(Mips::sub_hi, MVT::i32);
|
|
const SDValue Ops[] = { RegClass, Node->getOperand(0), LoIdx,
|
|
Node->getOperand(1), HiIdx };
|
|
SDNode *Res = CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL,
|
|
MVT::Untyped, Ops);
|
|
return std::make_pair(true, Res);
|
|
}
|
|
}
|
|
|
|
return std::make_pair(false, (SDNode*)NULL);
|
|
}
|
|
|
|
FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
|
|
return new MipsSEDAGToDAGISel(TM);
|
|
}
|