llvm-6502/test/CodeGen/ARM/2009-02-22-SoftenFloatVaArg.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

21 lines
600 B
LLVM

; RUN: llc < %s
; PR3610
target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-s0:0:64-f80:32:32"
target triple = "arm-elf"
define i32 @main(i8*) nounwind {
entry:
%ap = alloca i8* ; <i8**> [#uses=2]
store i8* %0, i8** %ap
%retval = alloca i32 ; <i32*> [#uses=2]
store i32 0, i32* %retval
%tmp = alloca float ; <float*> [#uses=1]
%1 = va_arg i8** %ap, float ; <float> [#uses=1]
store float %1, float* %tmp
br label %return
return: ; preds = %entry
%2 = load i32, i32* %retval ; <i32> [#uses=1]
ret i32 %2
}