llvm-6502/test/CodeGen/ARM/2013-01-21-PR14992.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

25 lines
944 B
LLVM

;PR14492 - Tablegen incorrectly converts ARM tLDMIA_UPD pseudo to tLDMIA
;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
;EXPECTED-LABEL: foo:
;CHECK-LABEL: foo:
define i32 @foo(i32* %a) nounwind optsize {
entry:
%0 = load i32, i32* %a, align 4
%arrayidx1 = getelementptr inbounds i32, i32* %a, i32 1
%1 = load i32, i32* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32* %a, i32 2
%2 = load i32, i32* %arrayidx2, align 4
%add.ptr = getelementptr inbounds i32, i32* %a, i32 3
;Make sure we do not have a duplicated register in the front of the reg list
;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
;CHECK-NOT: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], [[REG]],
tail call void @bar(i32* %add.ptr) nounwind optsize
%add = add nsw i32 %1, %0
%add3 = add nsw i32 %add, %2
ret i32 %add3
}
declare void @bar(i32*) optsize