llvm-6502/test/CodeGen/ARM/debug-frame-large-stack.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

83 lines
2.4 KiB
LLVM

; RUN: llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi -disable-fp-elim| FileCheck %s --check-prefix=CHECK-ARM
; RUN: llc -filetype=asm -o - < %s -mtriple arm-arm-netbsd-eabi | FileCheck %s --check-prefix=CHECK-ARM-FP-ELIM
define void @test1() {
%tmp = alloca [ 64 x i32 ] , align 4
ret void
}
; CHECK-ARM-LABEL: test1:
; CHECK-ARM: .cfi_startproc
; CHECK-ARM: sub sp, sp, #256
; CHECK-ARM: .cfi_endproc
; CHECK-ARM-FP-ELIM-LABEL: test1:
; CHECK-ARM-FP-ELIM: .cfi_startproc
; CHECK-ARM-FP-ELIM: sub sp, sp, #256
; CHECK-ARM-FP-ELIM: .cfi_endproc
define void @test2() {
%tmp = alloca [ 4168 x i8 ] , align 4
ret void
}
; CHECK-ARM-LABEL: test2:
; CHECK-ARM: .cfi_startproc
; CHECK-ARM: push {r4, r5}
; CHECK-ARM: .cfi_def_cfa_offset 8
; CHECK-ARM: .cfi_offset r5, -4
; CHECK-ARM: .cfi_offset r4, -8
; CHECK-ARM: sub sp, sp, #72
; CHECK-ARM: sub sp, sp, #4096
; CHECK-ARM: .cfi_def_cfa_offset 4176
; CHECK-ARM: .cfi_endproc
; CHECK-ARM-FP_ELIM-LABEL: test2:
; CHECK-ARM-FP_ELIM: .cfi_startproc
; CHECK-ARM-FP_ELIM: push {r4, r5}
; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 8
; CHECK-ARM-FP_ELIM: .cfi_offset 54, -4
; CHECK-ARM-FP_ELIM: .cfi_offset r4, -8
; CHECK-ARM-FP_ELIM: sub sp, sp, #72
; CHECK-ARM-FP_ELIM: sub sp, sp, #4096
; CHECK-ARM-FP_ELIM: .cfi_def_cfa_offset 4176
; CHECK-ARM-FP_ELIM: .cfi_endproc
define i32 @test3() {
%retval = alloca i32, align 4
%tmp = alloca i32, align 4
%a = alloca [805306369 x i8], align 16
store i32 0, i32* %tmp
%tmp1 = load i32, i32* %tmp
ret i32 %tmp1
}
; CHECK-ARM-LABEL: test3:
; CHECK-ARM: .cfi_startproc
; CHECK-ARM: push {r4, r5, r11}
; CHECK-ARM: .cfi_def_cfa_offset 12
; CHECK-ARM: .cfi_offset r11, -4
; CHECK-ARM: .cfi_offset r5, -8
; CHECK-ARM: .cfi_offset r4, -12
; CHECK-ARM: add r11, sp, #8
; CHECK-ARM: .cfi_def_cfa r11, 4
; CHECK-ARM: sub sp, sp, #20
; CHECK-ARM: sub sp, sp, #805306368
; CHECK-ARM: bic sp, sp, #15
; CHECK-ARM: .cfi_endproc
; CHECK-ARM-FP-ELIM-LABEL: test3:
; CHECK-ARM-FP-ELIM: .cfi_startproc
; CHECK-ARM-FP-ELIM: push {r4, r5, r11}
; CHECK-ARM-FP-ELIM: .cfi_def_cfa_offset 12
; CHECK-ARM-FP-ELIM: .cfi_offset r11, -4
; CHECK-ARM-FP-ELIM: .cfi_offset r5, -8
; CHECK-ARM-FP-ELIM: .cfi_offset r4, -12
; CHECK-ARM-FP-ELIM: add r11, sp, #8
; CHECK-ARM-FP-ELIM: .cfi_def_cfa r11, 4
; CHECK-ARM-FP-ELIM: sub sp, sp, #20
; CHECK-ARM-FP-ELIM: sub sp, sp, #805306368
; CHECK-ARM-FP-ELIM: bic sp, sp, #15
; CHECK-ARM-FP-ELIM: .cfi_endproc