mirror of
https://github.com/c64scene-ar/llvm-6502.git
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26d628d6ce
Summary: Currently fast-isel-abort will only abort for regular instructions, and just warn for function calls, terminators, function arguments. There is already fast-isel-abort-args but nothing for calls and terminators. This change turns the fast-isel-abort options into an integer option, so that multiple levels of strictness can be defined. This will help no being surprised when the "abort" option indeed does not abort, and enables the possibility to write test that verifies that no intrinsics are forgotten by fast-isel. Reviewers: resistor, echristo Subscribers: jfb, llvm-commits Differential Revision: http://reviews.llvm.org/D7941 From: Mehdi Amini <mehdi.amini@apple.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230775 91177308-0d34-0410-b5e6-96231b3b80d8
244 lines
6.0 KiB
LLVM
244 lines
6.0 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -verify-machineinstrs -O0 -fast-isel-abort=1 -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Test sitofp
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define void @sitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ARM: sitofp_single_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i32 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ARM: sitofp_single_i16
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; ARM: sxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i16
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; THUMB: sxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i16 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ARM: sitofp_single_i8
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; ARM: sxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.s32 s0, s0
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; THUMB: sitofp_single_i8
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; THUMB: sxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.s32 s0, s0
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%b.addr = alloca float, align 4
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%conv = sitofp i8 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @sitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i32 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i16
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; ARM: sxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i16
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; THUMB: sxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i16 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @sitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ARM: sitofp_double_i8
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; ARM: sxtb r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.s32 d16, s0
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; THUMB: sitofp_double_i8
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; THUMB: sxtb r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.s32 d16, s0
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%b.addr = alloca double, align 8
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%conv = sitofp i8 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test uitofp
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define void @uitofp_single_i32(i32 %a, float %b) nounwind ssp {
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entry:
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; ARM: uitofp_single_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i32 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i16(i16 %a, float %b) nounwind ssp {
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entry:
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; ARM: uitofp_single_i16
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; ARM: uxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i16
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; THUMB: uxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i16 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_single_i8(i8 %a) nounwind ssp {
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entry:
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; ARM: uitofp_single_i8
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; ARM: and r0, r0, #255
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; ARM: vmov s0, r0
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; ARM: vcvt.f32.u32 s0, s0
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; THUMB: uitofp_single_i8
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; THUMB: and r0, r0, #255
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f32.u32 s0, s0
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%b.addr = alloca float, align 4
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%conv = uitofp i8 %a to float
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store float %conv, float* %b.addr, align 4
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ret void
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}
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define void @uitofp_double_i32(i32 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i32
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i32
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i32 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i16(i16 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i16
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; ARM: uxth r0, r0
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i16
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; THUMB: uxth r0, r0
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i16 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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define void @uitofp_double_i8(i8 %a, double %b) nounwind ssp {
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entry:
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; ARM: uitofp_double_i8
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; ARM: and r0, r0, #255
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; ARM: vmov s0, r0
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; ARM: vcvt.f64.u32 d16, s0
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; THUMB: uitofp_double_i8
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; THUMB: and r0, r0, #255
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; THUMB: vmov s0, r0
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; THUMB: vcvt.f64.u32 d16, s0
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%b.addr = alloca double, align 8
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%conv = uitofp i8 %a to double
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store double %conv, double* %b.addr, align 8
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ret void
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}
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; Test fptosi
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define void @fptosi_float(float %a) nounwind ssp {
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entry:
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; ARM: fptosi_float
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; ARM: vcvt.s32.f32 s0, s0
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; THUMB: fptosi_float
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; THUMB: vcvt.s32.f32 s0, s0
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%b.addr = alloca i32, align 4
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%conv = fptosi float %a to i32
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store i32 %conv, i32* %b.addr, align 4
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ret void
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}
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define void @fptosi_double(double %a) nounwind ssp {
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entry:
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; ARM: fptosi_double
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; ARM: vcvt.s32.f64 s0, d16
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; THUMB: fptosi_double
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; THUMB: vcvt.s32.f64 s0, d16
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%b.addr = alloca i32, align 8
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%conv = fptosi double %a to i32
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store i32 %conv, i32* %b.addr, align 8
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ret void
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}
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; Test fptoui
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define void @fptoui_float(float %a) nounwind ssp {
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entry:
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; ARM: fptoui_float
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; ARM: vcvt.u32.f32 s0, s0
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; THUMB: fptoui_float
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; THUMB: vcvt.u32.f32 s0, s0
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%b.addr = alloca i32, align 4
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%conv = fptoui float %a to i32
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store i32 %conv, i32* %b.addr, align 4
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ret void
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}
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define void @fptoui_double(double %a) nounwind ssp {
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entry:
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; ARM: fptoui_double
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; ARM: vcvt.u32.f64 s0, d16
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; THUMB: fptoui_double
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; THUMB: vcvt.u32.f64 s0, d16
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%b.addr = alloca i32, align 8
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%conv = fptoui double %a to i32
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store i32 %conv, i32* %b.addr, align 8
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ret void
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}
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