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240b7f3324
The R0 register can now be allocated because instructions that cannot use R0 as a GPR have been appropriately marked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178123 91177308-0d34-0410-b5e6-96231b3b80d8
19 lines
629 B
LLVM
19 lines
629 B
LLVM
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s
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target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
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target triple = "powerpc64-unknown-linux-gnu"
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define i64 @foo(i64 %a) nounwind {
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entry:
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call void asm sideeffect "", "~{r3},~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{r12}"() nounwind
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br label %return
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; CHECK: @foo
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; Because r0 is allocatable, we can use it to hold r3 without spilling.
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; CHECK: mr 0, 3
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; CHECK: mr 3, 0
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return: ; preds = %entry
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ret i64 %a
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}
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