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5c8b83eb7a
The logic for expanding atomics that aren't natively supported in terms of cmpxchg loops is much simpler to express at the IR level. It also allows the normal optimisations and CodeGen improvements to help out with atomics, instead of using a limited set of possible instructions.. rdar://problem/13496295 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212119 91177308-0d34-0410-b5e6-96231b3b80d8
23 lines
573 B
LLVM
23 lines
573 B
LLVM
; RUN: llc < %s -mtriple=i386-apple-darwin -mcpu=corei7 | FileCheck %s
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; rdar://r7512579
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; PHI defs in the atomic loop should be used by the add / adc
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; instructions. They should not be dead.
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define void @t(i64* nocapture %p) nounwind ssp {
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entry:
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; CHECK-LABEL: t:
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; CHECK: movl ([[REG:%[a-z]+]]), %eax
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; CHECK: movl 4([[REG]]), %edx
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; CHECK: LBB0_1:
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; CHECK: movl %eax, %ebx
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; CHECK: addl $1, %ebx
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; CHECK: movl %edx, %ecx
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; CHECK: adcl $0, %ecx
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; CHECK: lock
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; CHECK-NEXT: cmpxchg8b ([[REG]])
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; CHECK-NEXT: jne
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%0 = atomicrmw add i64* %p, i64 1 seq_cst
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ret void
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}
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