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https://github.com/c64scene-ar/llvm-6502.git
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5335b49f96
We would emit a libcall for a 64-bit atomic on x86 after SVN r212119. This was due to the misuse of hasCmpxchg16 to indicate if cmpxchg8b was supported on a 32-bit target. They were added at different times and would result in the border condition being mishandled. This fixes the border case to emit the cmpxchg8b instruction for 64-bit atomic operations on x86 at the cost of restoring a long-standing bug in the codegen. We emit a cmpxchg8b on all x86 targets even where the CPU does not support this instruction (pre-Pentium CPUs). Although this bug should be fixed, this was present prior to SVN r212119 and this change, so this is not really introducing a regression. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@212956 91177308-0d34-0410-b5e6-96231b3b80d8
45 lines
1.1 KiB
LLVM
45 lines
1.1 KiB
LLVM
; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s
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; XFAIL: *
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define i64 @test_add(i64* %addr, i64 %inc) {
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; CHECK-LABEL: test_add:
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; CHECK: calll __sync_fetch_and_add_8
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%old = atomicrmw add i64* %addr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_sub(i64* %addr, i64 %inc) {
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; CHECK-LABEL: test_sub:
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; CHECK: calll __sync_fetch_and_sub_8
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%old = atomicrmw sub i64* %addr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_and(i64* %andr, i64 %inc) {
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; CHECK-LABEL: test_and:
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; CHECK: calll __sync_fetch_and_and_8
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%old = atomicrmw and i64* %andr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_or(i64* %orr, i64 %inc) {
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; CHECK-LABEL: test_or:
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; CHECK: calll __sync_fetch_and_or_8
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%old = atomicrmw or i64* %orr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_xor(i64* %xorr, i64 %inc) {
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; CHECK-LABEL: test_xor:
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; CHECK: calll __sync_fetch_and_xor_8
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%old = atomicrmw xor i64* %xorr, i64 %inc seq_cst
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ret i64 %old
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}
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define i64 @test_nand(i64* %nandr, i64 %inc) {
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; CHECK-LABEL: test_nand:
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; CHECK: calll __sync_fetch_and_nand_8
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%old = atomicrmw nand i64* %nandr, i64 %inc seq_cst
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ret i64 %old
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}
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