mirror of
https://github.com/c64scene-ar/llvm-6502.git
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7c9c6ed761
Essentially the same as the GEP change in r230786.
A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)
import fileinput
import sys
import re
pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")
for line in sys.stdin:
sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7649
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
95 lines
3.2 KiB
LLVM
95 lines
3.2 KiB
LLVM
; RUN: llc < %s -march=x86 -mtriple=i386-linux-gnu -mcpu=penryn -mattr=sse4.1 | FileCheck %s --check-prefix=X32
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; RUN: llc < %s -mtriple=x86_64-linux -mcpu=penryn -mattr=sse4.1 | FileCheck %s --check-prefix=X64
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; RUN: llc < %s -mtriple=x86_64-win32 -mcpu=penryn -mattr=sse4.1 | FileCheck %s --check-prefix=X64
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define i32 @test1() nounwind readonly {
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; X32-LABEL: test1:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl %gs:196, %eax
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; X32-NEXT: movl (%eax), %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test1:
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; X64: # BB#0: # %entry
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; X64-NEXT: movq %gs:320, %rax
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; X64-NEXT: movl (%rax), %eax
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; X64-NEXT: retq
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entry:
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%tmp = load i32*, i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1]
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%tmp1 = load i32, i32* %tmp ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i64 @test2(void (i8*)* addrspace(256)* %tmp8) nounwind {
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; X32-LABEL: test2:
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; X32: # BB#0: # %entry
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; X32-NEXT: subl $12, %esp
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: calll *%gs:(%eax)
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; X32-NEXT: xorl %eax, %eax
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; X32-NEXT: xorl %edx, %edx
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; X32-NEXT: addl $12, %esp
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; X32-NEXT: retl
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;
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; X64-LABEL: test2:
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; X64: # BB#0: # %entry
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; X64-NEXT: {{(subq.*%rsp|pushq)}}
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; X64-NEXT: callq *%gs:(%{{(rcx|rdi)}})
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; X64-NEXT: xorl %eax, %eax
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; X64-NEXT: {{(addq.*%rsp|popq)}}
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; X64-NEXT: retq
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entry:
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%tmp9 = load void (i8*)*, void (i8*)* addrspace(256)* %tmp8, align 8
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tail call void %tmp9(i8* undef) nounwind optsize
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ret i64 0
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}
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define <2 x i64> @pmovsxwd_1(i64 addrspace(256)* %p) nounwind readonly {
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; X32-LABEL: pmovsxwd_1:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: pmovsxwd %gs:(%eax), %xmm0
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; X32-NEXT: retl
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;
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; X64-LABEL: pmovsxwd_1:
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; X64: # BB#0: # %entry
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; X64-NEXT: pmovsxwd %gs:(%{{(rcx|rdi)}}), %xmm0
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; X64-NEXT: retq
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entry:
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%0 = load i64, i64 addrspace(256)* %p
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%tmp2 = insertelement <2 x i64> zeroinitializer, i64 %0, i32 0
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%1 = bitcast <2 x i64> %tmp2 to <8 x i16>
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%2 = tail call <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16> %1) nounwind readnone
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%3 = bitcast <4 x i32> %2 to <2 x i64>
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ret <2 x i64> %3
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}
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; The two loads here both look identical to selection DAG, except for their
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; address spaces. Make sure they aren't CSE'd.
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define i32 @test_no_cse() nounwind readonly {
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; X32-LABEL: test_no_cse:
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; X32: # BB#0: # %entry
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; X32-NEXT: movl %gs:196, %eax
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; X32-NEXT: movl (%eax), %eax
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; X32-NEXT: movl %fs:196, %ecx
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; X32-NEXT: addl (%ecx), %eax
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; X32-NEXT: retl
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;
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; X64-LABEL: test_no_cse:
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; X64: # BB#0: # %entry
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; X64-NEXT: movq %gs:320, %rax
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; X64-NEXT: movl (%rax), %eax
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; X64-NEXT: movq %fs:320, %rcx
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; X64-NEXT: addl (%rcx), %eax
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; X64-NEXT: retq
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entry:
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%tmp = load i32*, i32* addrspace(256)* getelementptr (i32* addrspace(256)* inttoptr (i32 72 to i32* addrspace(256)*), i32 31) ; <i32*> [#uses=1]
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%tmp1 = load i32, i32* %tmp ; <i32> [#uses=1]
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%tmp2 = load i32*, i32* addrspace(257)* getelementptr (i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31) ; <i32*> [#uses=1]
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%tmp3 = load i32, i32* %tmp2 ; <i32> [#uses=1]
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%tmp4 = add i32 %tmp1, %tmp3
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ret i32 %tmp4
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}
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declare <4 x i32> @llvm.x86.sse41.pmovsxwd(<8 x i16>) nounwind readnone
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