llvm-6502/test/CodeGen/X86/zext-extract_subreg.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

58 lines
1.9 KiB
LLVM

; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define void @t() nounwind ssp {
; CHECK-LABEL: t:
entry:
br i1 undef, label %return, label %if.end.i
if.end.i: ; preds = %entry
%tmp7.i = load i32, i32* undef, align 4
br i1 undef, label %return, label %if.end
if.end: ; preds = %if.end.i
; CHECK: %if.end
; CHECK: movl (%{{.*}}), [[REG:%[a-z]+]]
; CHECK-NOT: movl [[REG]], [[REG]]
; CHECK-NEXT: testl [[REG]], [[REG]]
; CHECK-NEXT: xorl
%tmp138 = select i1 undef, i32 0, i32 %tmp7.i
%tmp867 = zext i32 %tmp138 to i64
br label %while.cond
while.cond: ; preds = %while.body, %if.end
%tmp869 = sub i64 %tmp867, 0
%scale2.0 = trunc i64 %tmp869 to i32
%cmp149 = icmp eq i32 %scale2.0, 0
br i1 %cmp149, label %while.end, label %land.rhs
land.rhs: ; preds = %while.cond
br i1 undef, label %while.body, label %while.end
while.body: ; preds = %land.rhs
br label %while.cond
while.end: ; preds = %land.rhs, %while.cond
br i1 undef, label %cond.false205, label %cond.true190
cond.true190: ; preds = %while.end
br i1 undef, label %cond.false242, label %cond.true225
cond.false205: ; preds = %while.end
unreachable
cond.true225: ; preds = %cond.true190
br i1 undef, label %cond.false280, label %cond.true271
cond.false242: ; preds = %cond.true190
unreachable
cond.true271: ; preds = %cond.true225
unreachable
cond.false280: ; preds = %cond.true225
unreachable
return: ; preds = %if.end.i, %entry
ret void
}