mirror of
https://github.com/c64scene-ar/llvm-6502.git
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0b8c9a80f2
into their new header subdirectory: include/llvm/IR. This matches the directory structure of lib, and begins to correct a long standing point of file layout clutter in LLVM. There are still more header files to move here, but I wanted to handle them in separate commits to make tracking what files make sense at each layer easier. The only really questionable files here are the target intrinsic tablegen files. But that's a battle I'd rather not fight today. I've updated both CMake and Makefile build systems (I think, and my tests think, but I may have missed something). I've also re-sorted the includes throughout the project. I'll be committing updates to Clang, DragonEgg, and Polly momentarily. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
272 lines
10 KiB
C++
272 lines
10 KiB
C++
//===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
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// JIT-compile bitcode to native PowerPC.
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//
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//===----------------------------------------------------------------------===//
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#include "PPC.h"
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#include "PPCRelocations.h"
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#include "PPCTargetMachine.h"
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#include "llvm/CodeGen/JITCodeEmitter.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/IR/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetOptions.h"
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using namespace llvm;
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namespace {
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class PPCCodeEmitter : public MachineFunctionPass {
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TargetMachine &TM;
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JITCodeEmitter &MCE;
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MachineModuleInfo *MMI;
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void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineModuleInfo>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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static char ID;
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/// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
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/// its address in the function into this pointer.
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void *MovePCtoLROffset;
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public:
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PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
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: MachineFunctionPass(ID), TM(tm), MCE(mce) {}
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/// getBinaryCodeForInstr - This function, generated by the
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/// CodeEmitterGenerator using TableGen, produces the binary encoding for
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/// machine instructions.
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uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
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MachineRelocation GetRelocation(const MachineOperand &MO,
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unsigned RelocID) const;
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/// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
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unsigned getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const;
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unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
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unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
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const char *getPassName() const { return "PowerPC Machine Code Emitter"; }
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/// runOnMachineFunction - emits the given MachineFunction to memory
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///
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bool runOnMachineFunction(MachineFunction &MF);
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/// emitBasicBlock - emits the given MachineBasicBlock to memory
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///
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void emitBasicBlock(MachineBasicBlock &MBB);
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};
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}
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char PPCCodeEmitter::ID = 0;
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/// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
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/// to the specified MCE object.
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FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
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JITCodeEmitter &JCE) {
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return new PPCCodeEmitter(TM, JCE);
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}
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bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
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assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
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MF.getTarget().getRelocationModel() != Reloc::Static) &&
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"JIT relocation model must be set to static or default!");
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MMI = &getAnalysis<MachineModuleInfo>();
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MCE.setModuleInfo(MMI);
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do {
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MovePCtoLROffset = 0;
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MCE.startFunction(MF);
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for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
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emitBasicBlock(*BB);
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} while (MCE.finishFunction(MF));
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return false;
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}
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void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
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MCE.StartMachineBasicBlock(&MBB);
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for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
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const MachineInstr &MI = *I;
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MCE.processDebugLoc(MI.getDebugLoc(), true);
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switch (MI.getOpcode()) {
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default:
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MCE.emitWordBE(getBinaryCodeForInstr(MI));
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break;
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case TargetOpcode::PROLOG_LABEL:
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case TargetOpcode::EH_LABEL:
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MCE.emitLabel(MI.getOperand(0).getMCSymbol());
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break;
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case TargetOpcode::IMPLICIT_DEF:
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case TargetOpcode::KILL:
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break; // pseudo opcode, no side effects
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case PPC::MovePCtoLR:
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case PPC::MovePCtoLR8:
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assert(TM.getRelocationModel() == Reloc::PIC_);
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MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
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MCE.emitWordBE(0x48000005); // bl 1
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break;
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}
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MCE.processDebugLoc(MI.getDebugLoc(), false);
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}
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}
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unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
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unsigned OpNo) const {
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const MachineOperand &MO = MI.getOperand(OpNo);
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assert((MI.getOpcode() == PPC::MTCRF || MI.getOpcode() == PPC::MTCRF8 ||
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MI.getOpcode() == PPC::MFOCRF) &&
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(MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
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return 0x80 >> getPPCRegisterNumbering(MO.getReg());
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}
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MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
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unsigned RelocID) const {
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// If in PIC mode, we need to encode the negated address of the
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// 'movepctolr' into the unrelocated field. After relocation, we'll have
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// &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
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// field, we get &gv. This doesn't happen for branch relocations, which are
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// always implicitly pc relative.
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intptr_t Cst = 0;
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if (TM.getRelocationModel() == Reloc::PIC_) {
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assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
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Cst = -(intptr_t)MovePCtoLROffset - 4;
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}
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if (MO.isGlobal())
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return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
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const_cast<GlobalValue *>(MO.getGlobal()),
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Cst, isa<Function>(MO.getGlobal()));
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if (MO.isSymbol())
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return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
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RelocID, MO.getSymbolName(), Cst);
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if (MO.isCPI())
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return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
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RelocID, MO.getIndex(), Cst);
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if (MO.isMBB())
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return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
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RelocID, MO.getMBB());
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assert(MO.isJTI());
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return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
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RelocID, MO.getIndex(), Cst);
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}
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unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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const MachineOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
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MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
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return 0;
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}
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unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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const MachineOperand &MO = MI.getOperand(OpNo);
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MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
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return 0;
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}
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unsigned PPCCodeEmitter::getHA16Encoding(const MachineInstr &MI,
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unsigned OpNo) const {
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const MachineOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
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MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_high));
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return 0;
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}
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unsigned PPCCodeEmitter::getLO16Encoding(const MachineInstr &MI,
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unsigned OpNo) const {
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const MachineOperand &MO = MI.getOperand(OpNo);
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if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
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MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
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return 0;
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}
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unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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// Encode (imm, reg) as a memri, which has the low 16-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
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const MachineOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
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// Add a fixup for the displacement field.
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MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
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return RegBits;
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}
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unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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// Encode (imm, reg) as a memrix, which has the low 14-bits as the
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// displacement and the next 5 bits as the register #.
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assert(MI.getOperand(OpNo+1).isReg());
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unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
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const MachineOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm())
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return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits;
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MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
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return RegBits;
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}
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unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
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unsigned OpNo) const {
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llvm_unreachable("TLS not supported on the old JIT.");
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return 0;
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}
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unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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const MachineOperand &MO) const {
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if (MO.isReg()) {
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// MTCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
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// The GPR operand should come through here though.
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assert((MI.getOpcode() != PPC::MTCRF && MI.getOpcode() != PPC::MTCRF8 &&
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MI.getOpcode() != PPC::MFOCRF) ||
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MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
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return getPPCRegisterNumbering(MO.getReg());
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}
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assert(MO.isImm() &&
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"Relocation required in an instruction that we cannot encode!");
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return MO.getImm();
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}
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#include "PPCGenCodeEmitter.inc"
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