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2f7322b348
This patch introduces a new pass that computes the safe point to insert the
prologue and epilogue of the function.
The interest is to find safe points that are cheaper than the entry and exits
blocks.
As an example and to avoid regressions to be introduce, this patch also
implements the required bits to enable the shrink-wrapping pass for AArch64.
** Context **
Currently we insert the prologue and epilogue of the method/function in the
entry and exits blocks. Although this is correct, we can do a better job when
those are not immediately required and insert them at less frequently executed
places.
The job of the shrink-wrapping pass is to identify such places.
** Motivating example **
Let us consider the following function that perform a call only in one branch of
a if:
define i32 @f(i32 %a, i32 %b) {
%tmp = alloca i32, align 4
%tmp2 = icmp slt i32 %a, %b
br i1 %tmp2, label %true, label %false
true:
store i32 %a, i32* %tmp, align 4
%tmp4 = call i32 @doSomething(i32 0, i32* %tmp)
br label %false
false:
%tmp.0 = phi i32 [ %tmp4, %true ], [ %a, %0 ]
ret i32 %tmp.0
}
On AArch64 this code generates (removing the cfi directives to ease
readabilities):
_f: ; @f
; BB#0:
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
LBB0_2: ; %false
mov sp, x29
ldp x29, x30, [sp], #16
ret
With shrink-wrapping we could generate:
_f: ; @f
; BB#0:
cmp w0, w1
b.ge LBB0_2
; BB#1: ; %true
stp x29, x30, [sp, #-16]!
mov x29, sp
sub sp, sp, #16 ; =16
stur w0, [x29, #-4]
sub x1, x29, #4 ; =4
mov w0, wzr
bl _doSomething
add sp, x29, #16 ; =16
ldp x29, x30, [sp], #16
LBB0_2: ; %false
ret
Therefore, we would pay the overhead of setting up/destroying the frame only if
we actually do the call.
** Proposed Solution **
This patch introduces a new machine pass that perform the shrink-wrapping
analysis (See the comments at the beginning of ShrinkWrap.cpp for more details).
It then stores the safe save and restore point into the MachineFrameInfo
attached to the MachineFunction.
This information is then used by the PrologEpilogInserter (PEI) to place the
related code at the right place. This pass runs right before the PEI.
Unlike the original paper of Chow from PLDI’88, this implementation of
shrink-wrapping does not use expensive data-flow analysis and does not need hack
to properly avoid frequently executed point. Instead, it relies on dominance and
loop properties.
The pass is off by default and each target can opt-in by setting the
EnableShrinkWrap boolean to true in their derived class of TargetPassConfig.
This setting can also be overwritten on the command line by using
-enable-shrink-wrap.
Before you try out the pass for your target, make sure you properly fix your
emitProlog/emitEpilog/adjustForXXX method to cope with basic blocks that are not
necessarily the entry block.
** Design Decisions **
1. ShrinkWrap is its own pass right now. It could frankly be merged into PEI but
for debugging and clarity I thought it was best to have its own file.
2. Right now, we only support one save point and one restore point. At some
point we can expand this to several save point and restore point, the impacted
component would then be:
- The pass itself: New algorithm needed.
- MachineFrameInfo: Hold a list or set of Save/Restore point instead of one
pointer.
- PEI: Should loop over the save point and restore point.
Anyhow, at least for this first iteration, I do not believe this is interesting
to support the complex cases. We should revisit that when we motivating
examples.
Differential Revision: http://reviews.llvm.org/D9210
<rdar://problem/3201744>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236507 91177308-0d34-0410-b5e6-96231b3b80d8
113 lines
3.6 KiB
C++
113 lines
3.6 KiB
C++
//===----------------------- AMDGPUFrameLowering.cpp ----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//==-----------------------------------------------------------------------===//
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//
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// Interface to describe a layout of a stack frame on a AMDIL target machine
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUFrameLowering.h"
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#include "AMDGPURegisterInfo.h"
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#include "R600MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Instructions.h"
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using namespace llvm;
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AMDGPUFrameLowering::AMDGPUFrameLowering(StackDirection D, unsigned StackAl,
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int LAO, unsigned TransAl)
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: TargetFrameLowering(D, StackAl, LAO, TransAl) { }
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AMDGPUFrameLowering::~AMDGPUFrameLowering() { }
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unsigned AMDGPUFrameLowering::getStackWidth(const MachineFunction &MF) const {
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// XXX: Hardcoding to 1 for now.
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//
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// I think the StackWidth should stored as metadata associated with the
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// MachineFunction. This metadata can either be added by a frontend, or
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// calculated by a R600 specific LLVM IR pass.
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//
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// The StackWidth determines how stack objects are laid out in memory.
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// For a vector stack variable, like: int4 stack[2], the data will be stored
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// in the following ways depending on the StackWidth.
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//
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// StackWidth = 1:
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//
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// T0.X = stack[0].x
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// T1.X = stack[0].y
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// T2.X = stack[0].z
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// T3.X = stack[0].w
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// T4.X = stack[1].x
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// T5.X = stack[1].y
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// T6.X = stack[1].z
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// T7.X = stack[1].w
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//
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// StackWidth = 2:
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//
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// T0.X = stack[0].x
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// T0.Y = stack[0].y
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// T1.X = stack[0].z
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// T1.Y = stack[0].w
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// T2.X = stack[1].x
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// T2.Y = stack[1].y
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// T3.X = stack[1].z
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// T3.Y = stack[1].w
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//
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// StackWidth = 4:
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// T0.X = stack[0].x
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// T0.Y = stack[0].y
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// T0.Z = stack[0].z
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// T0.W = stack[0].w
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// T1.X = stack[1].x
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// T1.Y = stack[1].y
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// T1.Z = stack[1].z
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// T1.W = stack[1].w
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return 1;
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}
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/// \returns The number of registers allocated for \p FI.
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int AMDGPUFrameLowering::getFrameIndexOffset(const MachineFunction &MF,
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int FI) const {
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const MachineFrameInfo *MFI = MF.getFrameInfo();
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// Start the offset at 2 so we don't overwrite work group information.
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// XXX: We should only do this when the shader actually uses this
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// information.
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unsigned OffsetBytes = 2 * (getStackWidth(MF) * 4);
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int UpperBound = FI == -1 ? MFI->getNumObjects() : FI;
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for (int i = MFI->getObjectIndexBegin(); i < UpperBound; ++i) {
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OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(i));
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OffsetBytes += MFI->getObjectSize(i);
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// Each register holds 4 bytes, so we must always align the offset to at
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// least 4 bytes, so that 2 frame objects won't share the same register.
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OffsetBytes = RoundUpToAlignment(OffsetBytes, 4);
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}
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if (FI != -1)
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OffsetBytes = RoundUpToAlignment(OffsetBytes, MFI->getObjectAlignment(FI));
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return OffsetBytes / (getStackWidth(MF) * 4);
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}
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const TargetFrameLowering::SpillSlot *
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AMDGPUFrameLowering::getCalleeSavedSpillSlots(unsigned &NumEntries) const {
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NumEntries = 0;
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return nullptr;
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}
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void AMDGPUFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {}
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void
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AMDGPUFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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}
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bool
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AMDGPUFrameLowering::hasFP(const MachineFunction &MF) const {
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return false;
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}
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