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https://github.com/c64scene-ar/llvm-6502.git
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cac51be31f
The patch disabled unrolling in loop vectorization pass when VF==1 on x86 architecture, by setting MaxInterleaveFactor to 1. Unrolling in loop vectorization pass may introduce the cost of overflow check, memory boundary check and extra prologue/epilogue code when regular unroller will unroll the loop another time. Disable it when VF==1 remove the unnecessary cost on x86. The same can be done for other platforms after verifying interleaving/memory bound checking to be not perf critical on those platforms. Differential Revision: http://reviews.llvm.org/D9515 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236613 91177308-0d34-0410-b5e6-96231b3b80d8
79 lines
2.7 KiB
C++
79 lines
2.7 KiB
C++
//===-- AMDGPUTargetTransformInfo.h - AMDGPU specific TTI -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file a TargetTransformInfo::Concept conforming object specific to the
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/// AMDGPU target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_R600_AMDGPUTARGETTRANSFORMINFO_H
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#include "AMDGPU.h"
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#include "AMDGPUTargetMachine.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/Target/TargetLowering.h"
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namespace llvm {
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class AMDGPUTTIImpl : public BasicTTIImplBase<AMDGPUTTIImpl> {
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typedef BasicTTIImplBase<AMDGPUTTIImpl> BaseT;
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typedef TargetTransformInfo TTI;
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friend BaseT;
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const AMDGPUSubtarget *ST;
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const AMDGPUTargetLowering *TLI;
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const AMDGPUSubtarget *getST() const { return ST; }
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const AMDGPUTargetLowering *getTLI() const { return TLI; }
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public:
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explicit AMDGPUTTIImpl(const AMDGPUTargetMachine *TM)
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: BaseT(TM), ST(TM->getSubtargetImpl()), TLI(ST->getTargetLowering()) {}
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// Provide value semantics. MSVC requires that we spell all of these out.
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AMDGPUTTIImpl(const AMDGPUTTIImpl &Arg)
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: BaseT(static_cast<const BaseT &>(Arg)), ST(Arg.ST), TLI(Arg.TLI) {}
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AMDGPUTTIImpl(AMDGPUTTIImpl &&Arg)
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: BaseT(std::move(static_cast<BaseT &>(Arg))), ST(std::move(Arg.ST)),
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TLI(std::move(Arg.TLI)) {}
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AMDGPUTTIImpl &operator=(const AMDGPUTTIImpl &RHS) {
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BaseT::operator=(static_cast<const BaseT &>(RHS));
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ST = RHS.ST;
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TLI = RHS.TLI;
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return *this;
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}
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AMDGPUTTIImpl &operator=(AMDGPUTTIImpl &&RHS) {
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BaseT::operator=(std::move(static_cast<BaseT &>(RHS)));
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ST = std::move(RHS.ST);
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TLI = std::move(RHS.TLI);
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return *this;
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}
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bool hasBranchDivergence() { return true; }
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void getUnrollingPreferences(Loop *L, TTI::UnrollingPreferences &UP);
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TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth) {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return ST->hasBCNT(TyWidth) ? TTI::PSK_FastHardware : TTI::PSK_Software;
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}
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unsigned getNumberOfRegisters(bool Vector);
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unsigned getRegisterBitWidth(bool Vector);
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unsigned getMaxInterleaveFactor(unsigned VF);
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};
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} // end namespace llvm
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#endif
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