Ulrich Weigand 881a7154b9 Fix swapped BasePtr and Offset in pre-inc memory addresses. ... PPCTargetLowering::getPreIndexedAddressParts currently provides the base part of a memory address in the offset result, and the offset part in the base result. That swap is then undone again when an MI instruction is generated (in PPCDAGToDAGISel::Select for loads, and using .md Pat patterns for stores). This patch reverts this double swap, to make common code and back-end be in sync as to which part of the address is base and which is offset. To avoid performance regressions in certain cases, target code now checks whether the choice of base register would be rejected for pre-inc accesses by common code, and attempts to swap base and offset again in such cases. (Overall, this means that now pre-ice accesses are generated *more* frequently than before.) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8		2013-03-22 14:58:48 +00:00
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Analysis	Remove 'else' after 'return'.	2013-03-20 23:53:45 +00:00
Archive
AsmParser
Bitcode
CodeGen	Remove ScavengedRC from RegisterScavenging	2013-03-22 07:27:44 +00:00
DebugInfo	Fix missing std::. Not sure how this compiles for anyone else.	2013-03-21 00:57:21 +00:00
ExecutionEngine
IR	InstCombine: Improve the result bitvect type when folding (cmp pred (load (gep GV, i)) C) to a bit test.	2013-03-22 08:25:01 +00:00
Linker	The Linker interface has some dead code after the cleanup in r172749	2013-03-19 15:26:24 +00:00
MC	Dead code.	2013-03-19 22:13:05 +00:00
Object
Option
Support	Revert r177543: Add timing of the IR parsing code with a new	2013-03-22 02:20:34 +00:00
TableGen	Make sure TableGen exits with an error code after printing errors.	2013-03-20 20:43:11 +00:00
Target	Fix swapped BasePtr and Offset in pre-inc memory addresses.	2013-03-22 14:58:48 +00:00
Transforms	[asan] Change the way we report the alloca frame on stack-buff-overflow.	2013-03-22 10:37:20 +00:00
CMakeLists.txt
LLVMBuild.txt
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