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https://github.com/c64scene-ar/llvm-6502.git
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a551a48402
This patch allows llvm to recognize that a 64 bit object file is being produced and that the subsequently generated ELF header has the correct information. The test case checks for both big and little endian flavors. Patch by Jack Carter. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153889 91177308-0d34-0410-b5e6-96231b3b80d8
238 lines
8.0 KiB
C++
238 lines
8.0 KiB
C++
//===-- MipsASMBackend.cpp - Mips Asm Backend ----------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the MipsAsmBackend and MipsELFObjectWriter classes.
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//
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//===----------------------------------------------------------------------===//
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//
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#include "MipsBaseInfo.h"
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#include "MipsFixupKinds.h"
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#include "MCTargetDesc/MipsMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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// Prepare value for the target space for it
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static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
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// Add/subtract and shift
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switch (Kind) {
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default:
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return 0;
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case FK_GPRel_4:
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case FK_Data_4:
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case Mips::fixup_Mips_LO16:
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break;
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case Mips::fixup_Mips_PC16:
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// So far we are only using this type for branches.
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// For branches we start 1 instruction after the branch
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// so the displacement will be one instruction size less.
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Value -= 4;
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// The displacement is then divided by 4 to give us an 18 bit
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// address range.
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Value >>= 2;
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break;
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case Mips::fixup_Mips_26:
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// So far we are only using this type for jumps.
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// The displacement is then divided by 4 to give us an 28 bit
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// address range.
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Value >>= 2;
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break;
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case Mips::fixup_Mips_HI16:
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case Mips::fixup_Mips_GOT_Local:
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// Get the higher 16-bits. Also add 1 if bit 15 is 1.
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Value = ((Value + 0x8000) >> 16) & 0xffff;
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break;
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}
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return Value;
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}
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namespace {
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class MipsAsmBackend : public MCAsmBackend {
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Triple::OSType OSType;
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bool IsLittle; // Big or little endian
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bool Is64Bit; // 32 or 64 bit words
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public:
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MipsAsmBackend(const Target &T, Triple::OSType _OSType,
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bool _isLittle, bool _is64Bit)
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:MCAsmBackend(), OSType(_OSType), IsLittle(_isLittle), Is64Bit(_is64Bit) {}
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MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
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return createMipsELFObjectWriter(OS, OSType, IsLittle, Is64Bit);
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}
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/// ApplyFixup - Apply the \arg Value for given \arg Fixup into the provided
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/// data fragment, at the offset specified by the fixup and following the
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/// fixup kind as appropriate.
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void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
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uint64_t Value) const {
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MCFixupKind Kind = Fixup.getKind();
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Value = adjustFixupValue((unsigned)Kind, Value);
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int64_t SymOffset = MipsGetSymAndOffset(Fixup).second;
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if (!Value && !SymOffset)
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return; // Doesn't change encoding.
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// Where do we start in the object
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unsigned Offset = Fixup.getOffset();
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// Number of bytes we need to fixup
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unsigned NumBytes = (getFixupKindInfo(Kind).TargetSize + 7) / 8;
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// Used to point to big endian bytes
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unsigned FullSize;
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switch ((unsigned)Kind) {
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case Mips::fixup_Mips_16:
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FullSize = 2;
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break;
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case Mips::fixup_Mips_64:
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FullSize = 8;
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break;
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default:
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FullSize = 4;
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break;
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}
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// Grab current value, if any, from bits.
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uint64_t CurVal = 0;
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
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CurVal |= (uint64_t)((uint8_t)Data[Offset + Idx]) << (i*8);
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}
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uint64_t Mask = ((uint64_t)(-1) >> (64 - getFixupKindInfo(Kind).TargetSize));
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CurVal |= (Value + SymOffset) & Mask;
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// Write out the fixed up bytes back to the code/data bits.
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for (unsigned i = 0; i != NumBytes; ++i) {
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unsigned Idx = IsLittle ? i : (FullSize - 1 - i);
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Data[Offset + Idx] = (uint8_t)((CurVal >> (i*8)) & 0xff);
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}
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}
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unsigned getNumFixupKinds() const { return Mips::NumTargetFixupKinds; }
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
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const static MCFixupKindInfo Infos[Mips::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// MipsFixupKinds.h.
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//
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// name offset bits flags
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{ "fixup_Mips_16", 0, 16, 0 },
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{ "fixup_Mips_32", 0, 32, 0 },
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{ "fixup_Mips_REL32", 0, 32, 0 },
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{ "fixup_Mips_26", 0, 26, 0 },
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{ "fixup_Mips_HI16", 0, 16, 0 },
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{ "fixup_Mips_LO16", 0, 16, 0 },
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{ "fixup_Mips_GPREL16", 0, 16, 0 },
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{ "fixup_Mips_LITERAL", 0, 16, 0 },
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{ "fixup_Mips_GOT_Global", 0, 16, 0 },
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{ "fixup_Mips_GOT_Local", 0, 16, 0 },
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{ "fixup_Mips_PC16", 0, 16, MCFixupKindInfo::FKF_IsPCRel },
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{ "fixup_Mips_CALL16", 0, 16, 0 },
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{ "fixup_Mips_GPREL32", 0, 32, 0 },
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{ "fixup_Mips_SHIFT5", 6, 5, 0 },
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{ "fixup_Mips_SHIFT6", 6, 5, 0 },
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{ "fixup_Mips_64", 0, 64, 0 },
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{ "fixup_Mips_TLSGD", 0, 16, 0 },
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{ "fixup_Mips_GOTTPREL", 0, 16, 0 },
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{ "fixup_Mips_TPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_TPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_TLSLDM", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_HI", 0, 16, 0 },
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{ "fixup_Mips_DTPREL_LO", 0, 16, 0 },
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{ "fixup_Mips_Branch_PCRel", 0, 16, MCFixupKindInfo::FKF_IsPCRel }
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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/// @name Target Relaxation Interfaces
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/// @{
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/// MayNeedRelaxation - Check whether the given instruction may need
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/// relaxation.
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///
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/// \param Inst - The instruction to test.
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bool mayNeedRelaxation(const MCInst &Inst) const {
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return false;
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}
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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/// fixup requires the associated instruction to be relaxed.
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value,
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const MCInstFragment *DF,
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const MCAsmLayout &Layout) const {
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// FIXME.
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assert(0 && "RelaxInstruction() unimplemented");
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return false;
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}
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/// RelaxInstruction - Relax the instruction in the given fragment
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/// to the next wider instruction.
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///
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/// \param Inst - The instruction to relax, which may be the same
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/// as the output.
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/// \parm Res [output] - On return, the relaxed instruction.
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void relaxInstruction(const MCInst &Inst, MCInst &Res) const {
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}
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/// @}
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/// WriteNopData - Write an (optimal) nop sequence of Count bytes
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/// to the given output. If the target cannot generate such a sequence,
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/// it should return an error.
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///
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/// \return - True on success.
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bool writeNopData(uint64_t Count, MCObjectWriter *OW) const {
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return true;
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}
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}; // class MipsAsmBackend
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} // namespace
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// MCAsmBackend
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MCAsmBackend *llvm::createMipsAsmBackendEL32(const Target &T, StringRef TT) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/true, /*Is64Bit*/false);
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}
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MCAsmBackend *llvm::createMipsAsmBackendEB32(const Target &T, StringRef TT) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/false, /*Is64Bit*/false);
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}
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MCAsmBackend *llvm::createMipsAsmBackendEL64(const Target &T, StringRef TT) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/true, /*Is64Bit*/true);
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}
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MCAsmBackend *llvm::createMipsAsmBackendEB64(const Target &T, StringRef TT) {
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return new MipsAsmBackend(T, Triple(TT).getOS(),
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/*IsLittle*/false, /*Is64Bit*/true);
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}
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