llvm-6502/test/CodeGen/X86/addr-mode-matcher.ll
David Blaikie 7c9c6ed761 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-27 21:17:42 +00:00

63 lines
1.8 KiB
LLVM

; RUN: llc < %s | FileCheck %s
; This testcase used to hit an assert during ISel. For details, see the big
; comment inside the function.
; CHECK-LABEL: foo:
; The AND should be turned into a subreg access.
; CHECK-NOT: and
; The shift (leal) should be folded into the scale of the address in the load.
; CHECK-NOT: leal
; CHECK: movl {{.*}},4),
target datalayout = "e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128"
target triple = "i386-apple-macosx10.6.0"
define void @foo(i32 %a) {
bb:
br label %bb1692
bb1692:
%tmp1694 = phi i32 [ 0, %bb ], [ %tmp1745, %bb1692 ]
%xor = xor i32 0, %tmp1694
; %load1 = (load (and (shl %xor, 2), 1020))
%tmp1701 = shl i32 %xor, 2
%tmp1702 = and i32 %tmp1701, 1020
%tmp1703 = getelementptr inbounds [1028 x i8], [1028 x i8]* null, i32 0, i32 %tmp1702
%tmp1704 = bitcast i8* %tmp1703 to i32*
%load1 = load i32, i32* %tmp1704, align 4
; %load2 = (load (shl (and %xor, 255), 2))
%tmp1698 = and i32 %xor, 255
%tmp1706 = shl i32 %tmp1698, 2
%tmp1707 = getelementptr inbounds [1028 x i8], [1028 x i8]* null, i32 0, i32 %tmp1706
%tmp1708 = bitcast i8* %tmp1707 to i32*
%load2 = load i32, i32* %tmp1708, align 4
%tmp1710 = or i32 %load2, %a
; While matching xor we address-match %load1. The and-of-shift reassocication
; in address matching transform this into into a shift-of-and and the resuting
; node becomes identical to %load2. CSE replaces %load1 which leaves its
; references in MatchScope and RecordedNodes stale.
%tmp1711 = xor i32 %load1, %tmp1710
%tmp1744 = getelementptr inbounds [256 x i32], [256 x i32]* null, i32 0, i32 %tmp1711
store i32 0, i32* %tmp1744, align 4
%tmp1745 = add i32 %tmp1694, 1
indirectbr i8* undef, [label %bb1756, label %bb1692]
bb1756:
br label %bb2705
bb2705:
indirectbr i8* undef, [label %bb5721, label %bb5736]
bb5721:
br label %bb2705
bb5736:
ret void
}