mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
1726e2ff15
This patch teaches the backend how to simplify/canonicalize dag node
sequences normally introduced by the backend when promoting certain dag nodes
with illegal vector type.
This patch adds two new combine rules:
1) fold (shuffle (bitcast (BINOP A, B)), Undef, <Mask>) ->
(shuffle (BINOP (bitcast A), (bitcast B)), Undef, <Mask>)
2) fold (BINOP (shuffle (A, Undef, <Mask>)), (shuffle (B, Undef, <Mask>))) ->
(shuffle (BINOP A, B), Undef, <Mask>).
Both rules are only triggered on the type-legalized DAG.
In particular, rule 1. is a target specific combine rule that attempts
to sink a bitconvert into the operands of a binary operation.
Rule 2. is a target independet rule that attempts to move a shuffle
immediately after a binary operation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209930 91177308-0d34-0410-b5e6-96231b3b80d8
274 lines
6.2 KiB
LLVM
274 lines
6.2 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=SSE41
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; RUN: llc < %s -march=x86-64 -mcpu=corei7-avx -mtriple=x86_64-unknown-linux-gnu | FileCheck %s -check-prefix=CHECK -check-prefix=AVX
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define double @test1_add(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%add = add <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %add to double
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ret double %3
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}
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; CHECK-LABEL: test1_add
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; SSE41: paddd
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; AVX: vpaddd
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; CHECK-NEXT: ret
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define double @test2_add(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%add = add <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %add to double
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ret double %3
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}
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; CHECK-LABEL: test2_add
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; SSE41: paddw
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; AVX: vpaddw
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; CHECK-NEXT: ret
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define double @test3_add(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%add = add <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %add to double
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ret double %3
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}
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; CHECK-LABEL: test3_add
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; SSE41: paddb
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; AVX: vpaddb
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; CHECK-NEXT: ret
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define double @test1_sub(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%sub = sub <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test1_sub
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; SSE41: psubd
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; AVX: vpsubd
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; CHECK-NEXT: ret
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define double @test2_sub(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%sub = sub <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test2_sub
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; SSE41: psubw
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; AVX: vpsubw
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; CHECK-NEXT: ret
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define double @test3_sub(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%sub = sub <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test3_sub
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; SSE41: psubb
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; AVX: vpsubb
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; CHECK-NEXT: ret
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define double @test1_mul(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%mul = mul <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test1_mul
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; SSE41: pmulld
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; AVX: vpmulld
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; CHECK-NEXT: ret
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define double @test2_mul(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%mul = mul <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test2_mul
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; SSE41: pmullw
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; AVX: vpmullw
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; CHECK-NEXT: ret
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; There is no legal ISD::MUL with type MVT::v8i16.
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define double @test3_mul(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%mul = mul <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test3_mul
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; CHECK: pmullw
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; CHECK-NEXT: pshufb
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; CHECK-NEXT: ret
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define double @test1_and(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%and = and <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %and to double
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ret double %3
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}
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; CHECK-LABEL: test1_and
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; SSE41: andps
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; AVX: vandps
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; CHECK-NEXT: ret
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define double @test2_and(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%and = and <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %and to double
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ret double %3
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}
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; CHECK-LABEL: test2_and
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; SSE41: andps
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; AVX: vandps
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; CHECK-NEXT: ret
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define double @test3_and(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%and = and <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %and to double
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ret double %3
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}
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; CHECK-LABEL: test3_and
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; SSE41: andps
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; AVX: vandps
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; CHECK-NEXT: ret
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define double @test1_or(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%or = or <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %or to double
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ret double %3
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}
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; CHECK-LABEL: test1_or
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; SSE41: orps
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; AVX: vorps
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; CHECK-NEXT: ret
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define double @test2_or(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%or = or <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %or to double
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ret double %3
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}
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; CHECK-LABEL: test2_or
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; SSE41: orps
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; AVX: vorps
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; CHECK-NEXT: ret
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define double @test3_or(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%or = or <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %or to double
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ret double %3
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}
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; CHECK-LABEL: test3_or
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; SSE41: orps
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; AVX: vorps
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; CHECK-NEXT: ret
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define double @test1_xor(double %A, double %B) {
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%1 = bitcast double %A to <2 x i32>
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%2 = bitcast double %B to <2 x i32>
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%xor = xor <2 x i32> %1, %2
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%3 = bitcast <2 x i32> %xor to double
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ret double %3
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}
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; CHECK-LABEL: test1_xor
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; SSE41: xorps
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; AVX: vxorps
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; CHECK-NEXT: ret
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define double @test2_xor(double %A, double %B) {
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%1 = bitcast double %A to <4 x i16>
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%2 = bitcast double %B to <4 x i16>
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%xor = xor <4 x i16> %1, %2
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%3 = bitcast <4 x i16> %xor to double
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ret double %3
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}
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; CHECK-LABEL: test2_xor
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; SSE41: xorps
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; AVX: vxorps
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; CHECK-NEXT: ret
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define double @test3_xor(double %A, double %B) {
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%1 = bitcast double %A to <8 x i8>
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%2 = bitcast double %B to <8 x i8>
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%xor = xor <8 x i8> %1, %2
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%3 = bitcast <8 x i8> %xor to double
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ret double %3
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}
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; CHECK-LABEL: test3_xor
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; SSE41: xorps
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; AVX: vxorps
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; CHECK-NEXT: ret
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define double @test_fadd(double %A, double %B) {
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%1 = bitcast double %A to <2 x float>
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%2 = bitcast double %B to <2 x float>
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%add = fadd <2 x float> %1, %2
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%3 = bitcast <2 x float> %add to double
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ret double %3
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}
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; CHECK-LABEL: test_fadd
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; SSE41: addps
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; AVX: vaddps
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; CHECK-NEXT: ret
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define double @test_fsub(double %A, double %B) {
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%1 = bitcast double %A to <2 x float>
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%2 = bitcast double %B to <2 x float>
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%sub = fsub <2 x float> %1, %2
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%3 = bitcast <2 x float> %sub to double
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ret double %3
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}
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; CHECK-LABEL: test_fsub
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; SSE41: subps
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; AVX: vsubps
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; CHECK-NEXT: ret
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define double @test_fmul(double %A, double %B) {
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%1 = bitcast double %A to <2 x float>
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%2 = bitcast double %B to <2 x float>
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%mul = fmul <2 x float> %1, %2
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%3 = bitcast <2 x float> %mul to double
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ret double %3
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}
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; CHECK-LABEL: test_fmul
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; SSE41: mulps
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; AVX: vmulps
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; CHECK-NEXT: ret
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