mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-15 20:29:48 +00:00
a77462187f
It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237792 91177308-0d34-0410-b5e6-96231b3b80d8
158 lines
3.7 KiB
LLVM
158 lines
3.7 KiB
LLVM
; RUN: llc -O1 < %s -march=mips64 -mcpu=octeon | FileCheck %s -check-prefix=ALL -check-prefix=OCTEON
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; RUN: llc -O1 < %s -march=mips64 -mcpu=mips64 | FileCheck %s -check-prefix=ALL -check-prefix=MIPS64
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define i64 @addi64(i64 %a, i64 %b) nounwind {
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entry:
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; ALL-LABEL: addi64:
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; OCTEON: jr $ra
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; OCTEON: baddu $2, $4, $5
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; MIPS64: daddu $[[T0:[0-9]+]], $4, $5
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; MIPS64: jr $ra
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; MIPS64: andi $2, $[[T0]], 255
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%add = add i64 %a, %b
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%and = and i64 %add, 255
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ret i64 %and
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}
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define i64 @mul(i64 %a, i64 %b) nounwind {
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entry:
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; ALL-LABEL: mul:
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; OCTEON: jr $ra
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; OCTEON: dmul $2, $4, $5
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; MIPS64: dmult $4, $5
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; MIPS64: jr $ra
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; MIPS64: mflo $2
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%res = mul i64 %a, %b
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ret i64 %res
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}
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define i64 @cmpeq(i64 %a, i64 %b) nounwind {
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entry:
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; ALL-LABEL: cmpeq:
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; OCTEON: jr $ra
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; OCTEON: seq $2, $4, $5
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; MIPS64: xor $[[T0:[0-9]+]], $4, $5
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; MIPS64: sltiu $[[T1:[0-9]+]], $[[T0]], 1
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; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
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; MIPS64: jr $ra
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; MIPS64: dsrl $2, $[[T2]], 32
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%res = icmp eq i64 %a, %b
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%res2 = zext i1 %res to i64
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ret i64 %res2
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}
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define i64 @cmpeqi(i64 %a) nounwind {
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entry:
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; ALL-LABEL: cmpeqi:
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; OCTEON: jr $ra
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; OCTEON: seqi $2, $4, 42
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; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
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; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
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; MIPS64: sltiu $[[T2:[0-9]+]], $[[T1]], 1
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; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
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; MIPS64: jr $ra
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; MIPS64: dsrl $2, $[[T3]], 32
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%res = icmp eq i64 %a, 42
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%res2 = zext i1 %res to i64
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ret i64 %res2
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}
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define i64 @cmpne(i64 %a, i64 %b) nounwind {
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entry:
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; ALL-LABEL: cmpne:
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; OCTEON: jr $ra
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; OCTEON: sne $2, $4, $5
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; MIPS64: xor $[[T0:[0-9]+]], $4, $5
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; MIPS64: sltu $[[T1:[0-9]+]], $zero, $[[T0]]
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; MIPS64: dsll $[[T2:[0-9]+]], $[[T1]], 32
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; MIPS64: jr $ra
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; MIPS64: dsrl $2, $[[T2]], 32
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%res = icmp ne i64 %a, %b
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%res2 = zext i1 %res to i64
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ret i64 %res2
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}
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define i64 @cmpnei(i64 %a) nounwind {
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entry:
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; ALL-LABEL: cmpnei:
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; OCTEON: jr $ra
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; OCTEON: snei $2, $4, 42
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; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 42
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; MIPS64: xor $[[T1:[0-9]+]], $4, $[[T0]]
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; MIPS64: sltu $[[T2:[0-9]+]], $zero, $[[T1]]
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; MIPS64: dsll $[[T3:[0-9]+]], $[[T2]], 32
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; MIPS64: jr $ra
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; MIPS64: dsrl $2, $[[T3]], 32
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%res = icmp ne i64 %a, 42
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%res2 = zext i1 %res to i64
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ret i64 %res2
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}
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define i64 @bbit0(i64 %a) nounwind {
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entry:
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; ALL-LABEL: bbit0:
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; OCTEON: bbit0 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64: andi $[[T0:[0-9]+]], $4, 8
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; MIPS64: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 8
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%res = icmp eq i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit032(i64 %a) nounwind {
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entry:
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; ALL-LABEL: bbit032:
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; OCTEON: bbit032 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
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; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
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; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
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; MIPS64: bnez $[[T2]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 34359738368
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%res = icmp eq i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit1(i64 %a) nounwind {
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entry:
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; ALL-LABEL: bbit1:
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; OCTEON: bbit1 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64: andi $[[T0:[0-9]+]], $4, 8
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; MIPS64: beqz $[[T0]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 8
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%res = icmp ne i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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define i64 @bbit132(i64 %a) nounwind {
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entry:
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; ALL-LABEL: bbit132:
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; OCTEON: bbit132 $4, 3, $[[BB0:BB[0-9_]+]]
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; MIPS64: daddiu $[[T0:[0-9]+]], $zero, 1
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; MIPS64: dsll $[[T1:[0-9]+]], $[[T0]], 35
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; MIPS64: and $[[T2:[0-9]+]], $4, $[[T1]]
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; MIPS64: beqz $[[T2]], $[[BB0:BB[0-9_]+]]
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%bit = and i64 %a, 34359738368
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%res = icmp ne i64 %bit, 0
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br i1 %res, label %endif, label %if
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if:
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ret i64 48
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endif:
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ret i64 12
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}
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