mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-29 13:29:28 +00:00
-- C.4 and C.5 statements, when NSAA is not equal to SP. -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a variadic procedure. Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are some exceptions in AAPCS. 1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs. 2. Check that for VA functions all params uses GPRs and then stack. No exceptions, no CPRCs here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180011 91177308-0d34-0410-b5e6-96231b3b80d8
166 lines
6.0 KiB
C++
166 lines
6.0 KiB
C++
//=== ARMCallingConv.h - ARM Custom Calling Convention Routines -*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file contains the custom routines for the ARM Calling Convention that
|
|
// aren't done by tablegen.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef ARMCALLINGCONV_H
|
|
#define ARMCALLINGCONV_H
|
|
|
|
#include "ARM.h"
|
|
#include "ARMBaseInstrInfo.h"
|
|
#include "ARMSubtarget.h"
|
|
#include "llvm/CodeGen/CallingConvLower.h"
|
|
#include "llvm/IR/CallingConv.h"
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
|
|
namespace llvm {
|
|
|
|
// APCS f64 is in register pairs, possibly split to stack
|
|
static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
CCState &State, bool CanFail) {
|
|
static const uint16_t RegList[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
|
|
|
|
// Try to get the first register.
|
|
if (unsigned Reg = State.AllocateReg(RegList, 4))
|
|
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
|
else {
|
|
// For the 2nd half of a v2f64, do not fail.
|
|
if (CanFail)
|
|
return false;
|
|
|
|
// Put the whole thing on the stack.
|
|
State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
|
|
State.AllocateStack(8, 4),
|
|
LocVT, LocInfo));
|
|
return true;
|
|
}
|
|
|
|
// Try to get the second register.
|
|
if (unsigned Reg = State.AllocateReg(RegList, 4))
|
|
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
|
else
|
|
State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
|
|
State.AllocateStack(4, 4),
|
|
LocVT, LocInfo));
|
|
return true;
|
|
}
|
|
|
|
static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
ISD::ArgFlagsTy &ArgFlags,
|
|
CCState &State) {
|
|
if (!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
|
|
return false;
|
|
if (LocVT == MVT::v2f64 &&
|
|
!f64AssignAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
|
|
return false;
|
|
return true; // we handled it
|
|
}
|
|
|
|
// AAPCS f64 is in aligned register pairs
|
|
static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
CCState &State, bool CanFail) {
|
|
static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
|
|
static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
|
|
static const uint16_t ShadowRegList[] = { ARM::R0, ARM::R1 };
|
|
static const uint16_t GPRArgRegs[] = { ARM::R0, ARM::R1, ARM::R2, ARM::R3 };
|
|
|
|
unsigned Reg = State.AllocateReg(HiRegList, ShadowRegList, 2);
|
|
if (Reg == 0) {
|
|
|
|
// If we had R3 unallocated only, now we still must to waste it.
|
|
Reg = State.AllocateReg(GPRArgRegs, 4);
|
|
assert((!Reg || Reg == ARM::R3) && "Wrong GPRs usage for f64");
|
|
|
|
// For the 2nd half of a v2f64, do not just fail.
|
|
if (CanFail)
|
|
return false;
|
|
|
|
// Put the whole thing on the stack.
|
|
State.addLoc(CCValAssign::getCustomMem(ValNo, ValVT,
|
|
State.AllocateStack(8, 8),
|
|
LocVT, LocInfo));
|
|
return true;
|
|
}
|
|
|
|
unsigned i;
|
|
for (i = 0; i < 2; ++i)
|
|
if (HiRegList[i] == Reg)
|
|
break;
|
|
|
|
unsigned T = State.AllocateReg(LoRegList[i]);
|
|
(void)T;
|
|
assert(T == LoRegList[i] && "Could not allocate register");
|
|
|
|
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
|
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
|
|
LocVT, LocInfo));
|
|
return true;
|
|
}
|
|
|
|
static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
ISD::ArgFlagsTy &ArgFlags,
|
|
CCState &State) {
|
|
if (!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, true))
|
|
return false;
|
|
if (LocVT == MVT::v2f64 &&
|
|
!f64AssignAAPCS(ValNo, ValVT, LocVT, LocInfo, State, false))
|
|
return false;
|
|
return true; // we handled it
|
|
}
|
|
|
|
static bool f64RetAssign(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo, CCState &State) {
|
|
static const uint16_t HiRegList[] = { ARM::R0, ARM::R2 };
|
|
static const uint16_t LoRegList[] = { ARM::R1, ARM::R3 };
|
|
|
|
unsigned Reg = State.AllocateReg(HiRegList, LoRegList, 2);
|
|
if (Reg == 0)
|
|
return false; // we didn't handle it
|
|
|
|
unsigned i;
|
|
for (i = 0; i < 2; ++i)
|
|
if (HiRegList[i] == Reg)
|
|
break;
|
|
|
|
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
|
State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, LoRegList[i],
|
|
LocVT, LocInfo));
|
|
return true;
|
|
}
|
|
|
|
static bool RetCC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
ISD::ArgFlagsTy &ArgFlags,
|
|
CCState &State) {
|
|
if (!f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
|
|
return false;
|
|
if (LocVT == MVT::v2f64 && !f64RetAssign(ValNo, ValVT, LocVT, LocInfo, State))
|
|
return false;
|
|
return true; // we handled it
|
|
}
|
|
|
|
static bool RetCC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
|
CCValAssign::LocInfo &LocInfo,
|
|
ISD::ArgFlagsTy &ArgFlags,
|
|
CCState &State) {
|
|
return RetCC_ARM_APCS_Custom_f64(ValNo, ValVT, LocVT, LocInfo, ArgFlags,
|
|
State);
|
|
}
|
|
|
|
} // End llvm namespace
|
|
|
|
#endif
|