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Changing ARMBaseTargetMachine to return ARMTargetLowering intead of the generic one (similar to x86 code). Tests showing which instructions were added to cast when necessary or cost zero when not. Downcast to 16 bits are not lowered in NEON, so costs are not there yet. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173849 91177308-0d34-0410-b5e6-96231b3b80d8
147 lines
4.7 KiB
C++
147 lines
4.7 KiB
C++
//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the ARM specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef ARMTARGETMACHINE_H
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#define ARMTARGETMACHINE_H
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#include "ARMFrameLowering.h"
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#include "ARMISelLowering.h"
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#include "ARMInstrInfo.h"
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#include "ARMJITInfo.h"
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#include "ARMSelectionDAGInfo.h"
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#include "ARMSubtarget.h"
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#include "Thumb1FrameLowering.h"
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#include "Thumb1InstrInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/ADT/OwningPtr.h"
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#include "llvm/IR/DataLayout.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/Target/TargetMachine.h"
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namespace llvm {
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class ARMBaseTargetMachine : public LLVMTargetMachine {
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protected:
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ARMSubtarget Subtarget;
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private:
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ARMJITInfo JITInfo;
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InstrItineraryData InstrItins;
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public:
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ARMBaseTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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virtual ARMJITInfo *getJITInfo() { return &JITInfo; }
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virtual const ARMSubtarget *getSubtargetImpl() const { return &Subtarget; }
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virtual const ARMTargetLowering *getTargetLowering() const {
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// Implemented by derived classes
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llvm_unreachable("getTargetLowering not implemented");
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}
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virtual const InstrItineraryData *getInstrItineraryData() const {
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return &InstrItins;
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}
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/// \brief Register ARM analysis passes with a pass manager.
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virtual void addAnalysisPasses(PassManagerBase &PM);
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// Pass Pipeline Configuration
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virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
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virtual bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &MCE);
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};
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/// ARMTargetMachine - ARM target machine.
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///
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class ARMTargetMachine : public ARMBaseTargetMachine {
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virtual void anchor();
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ARMInstrInfo InstrInfo;
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const DataLayout DL; // Calculates type size & alignment
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ARMTargetLowering TLInfo;
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ARMSelectionDAGInfo TSInfo;
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ARMFrameLowering FrameLowering;
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public:
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ARMTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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virtual const ARMRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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virtual const ARMTargetLowering *getTargetLowering() const {
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return &TLInfo;
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}
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virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
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return &TSInfo;
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}
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virtual const ARMFrameLowering *getFrameLowering() const {
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return &FrameLowering;
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}
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virtual const ARMInstrInfo *getInstrInfo() const { return &InstrInfo; }
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virtual const DataLayout *getDataLayout() const { return &DL; }
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};
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/// ThumbTargetMachine - Thumb target machine.
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/// Due to the way architectures are handled, this represents both
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/// Thumb-1 and Thumb-2.
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///
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class ThumbTargetMachine : public ARMBaseTargetMachine {
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virtual void anchor();
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// Either Thumb1InstrInfo or Thumb2InstrInfo.
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OwningPtr<ARMBaseInstrInfo> InstrInfo;
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const DataLayout DL; // Calculates type size & alignment
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ARMTargetLowering TLInfo;
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ARMSelectionDAGInfo TSInfo;
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// Either Thumb1FrameLowering or ARMFrameLowering.
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OwningPtr<ARMFrameLowering> FrameLowering;
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public:
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ThumbTargetMachine(const Target &T, StringRef TT,
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StringRef CPU, StringRef FS,
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const TargetOptions &Options,
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Reloc::Model RM, CodeModel::Model CM,
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CodeGenOpt::Level OL);
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/// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
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virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
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return &InstrInfo->getRegisterInfo();
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}
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virtual const ARMTargetLowering *getTargetLowering() const {
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return &TLInfo;
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}
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virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
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return &TSInfo;
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}
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/// returns either Thumb1InstrInfo or Thumb2InstrInfo
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virtual const ARMBaseInstrInfo *getInstrInfo() const {
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return InstrInfo.get();
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}
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/// returns either Thumb1FrameLowering or ARMFrameLowering
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virtual const ARMFrameLowering *getFrameLowering() const {
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return FrameLowering.get();
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}
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virtual const DataLayout *getDataLayout() const { return &DL; }
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};
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} // end namespace llvm
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#endif
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