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3f05a5e0ad
Other f64 opcodes not supported on SI can be lowered in a similar way. v2: use complex VOP3 patterns git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@233076 91177308-0d34-0410-b5e6-96231b3b80d8
61 lines
3.4 KiB
LLVM
61 lines
3.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -enable-unsafe-fp-math < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=FUNC %s
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declare double @llvm.fabs.f64(double %Val)
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declare double @llvm.AMDGPU.fract.f64(double) nounwind readnone
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; FUNC-LABEL: {{^}}fract_f64:
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; GCN: v_fract_f64_e32 [[FRC:v\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
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%val = load double, double addrspace(1)* %src, align 4
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%fract = call double @llvm.AMDGPU.fract.f64(double %val) nounwind readnone
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store double %fract, double addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fract_f64_neg:
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; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
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%val = load double, double addrspace(1)* %src, align 4
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%neg = fsub double 0.0, %val
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%fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
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store double %fract, double addrspace(1)* %out, align 4
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ret void
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}
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; FUNC-LABEL: {{^}}fract_f64_neg_abs:
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; GCN: v_fract_f64_e64 [[FRC:v\[[0-9]+:[0-9]+\]]], -|v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]]|
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; SI: v_mov_b32_e32 v[[UPLO:[0-9]+]], -1
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; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
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; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
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; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
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; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
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; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
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; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
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; CI: buffer_store_dwordx2 [[FRC]]
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define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
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%val = load double, double addrspace(1)* %src, align 4
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%abs = call double @llvm.fabs.f64(double %val)
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%neg = fsub double 0.0, %abs
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%fract = call double @llvm.AMDGPU.fract.f64(double %neg) nounwind readnone
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store double %fract, double addrspace(1)* %out, align 4
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ret void
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}
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