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https://github.com/c64scene-ar/llvm-6502.git
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f17a95a681
When SI_KILL has a register operand, its lowered form writes to vcc. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236307 91177308-0d34-0410-b5e6-96231b3b80d8
40 lines
1.6 KiB
LLVM
40 lines
1.6 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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; SI-LABEL: {{^}}kill_gs_const:
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; SI-NOT: v_cmpx_le_f32
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; SI: s_mov_b64 exec, 0
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define void @kill_gs_const() #0 {
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main_body:
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%0 = icmp ule i32 0, 3
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%1 = select i1 %0, float 1.000000e+00, float -1.000000e+00
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call void @llvm.AMDGPU.kill(float %1)
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%2 = icmp ule i32 3, 0
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%3 = select i1 %2, float 1.000000e+00, float -1.000000e+00
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call void @llvm.AMDGPU.kill(float %3)
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ret void
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}
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; SI-LABEL: {{^}}kill_vcc_implicit_def:
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; SI-NOT: v_cmp_gt_f32_e32 vcc,
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; SI: v_cmp_gt_f32_e64 [[CMP:s\[[0-9]+:[0-9]+\]]], 0, v{{[0-9]+}}
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; SI: v_cmpx_le_f32_e32 vcc, 0, v{{[0-9]+}}
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; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1.0, [[CMP]]
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define void @kill_vcc_implicit_def([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) #1 {
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entry:
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%tmp0 = fcmp olt float %13, 0.0
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call void @llvm.AMDGPU.kill(float %14)
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%tmp1 = select i1 %tmp0, float 1.0, float 0.0
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 1, i32 1, float %tmp1, float %tmp1, float %tmp1, float %tmp1)
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ret void
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}
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declare void @llvm.AMDGPU.kill(float)
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { "ShaderType"="2" }
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attributes #1 = { "ShaderType"="0" }
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!0 = !{!"const", null, i32 1}
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