mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-09-03 02:30:00 +00:00
b834f5d13d
something totally broken and parsing them as immediates, but the .td file also had the wrong match class so things sortof worked. Except, that is, that we would parse movl $0, %eax as movl 0, %eax Feel free to guess how well that worked. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94869 91177308-0d34-0410-b5e6-96231b3b80d8
533 lines
16 KiB
C++
533 lines
16 KiB
C++
//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Target/TargetAsmParser.h"
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#include "X86.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Twine.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCAsmLexer.h"
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#include "llvm/MC/MCParser/MCAsmParser.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/Support/SourceMgr.h"
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#include "llvm/Target/TargetRegistry.h"
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#include "llvm/Target/TargetAsmParser.h"
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using namespace llvm;
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namespace {
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struct X86Operand;
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class X86ATTAsmParser : public TargetAsmParser {
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MCAsmParser &Parser;
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private:
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MCAsmParser &getParser() const { return Parser; }
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MCAsmLexer &getLexer() const { return Parser.getLexer(); }
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void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
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bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
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X86Operand *ParseOperand();
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X86Operand *ParseMemOperand();
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bool ParseDirectiveWord(unsigned Size, SMLoc L);
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/// @name Auto-generated Match Functions
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/// {
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bool MatchInstruction(const SmallVectorImpl<MCParsedAsmOperand*> &Operands,
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MCInst &Inst);
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/// }
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public:
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X86ATTAsmParser(const Target &T, MCAsmParser &_Parser)
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: TargetAsmParser(T), Parser(_Parser) {}
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virtual bool ParseInstruction(const StringRef &Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands);
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virtual bool ParseDirective(AsmToken DirectiveID);
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};
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} // end anonymous namespace
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/// @name Auto-generated Match Functions
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/// {
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static unsigned MatchRegisterName(const StringRef &Name);
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/// }
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namespace {
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/// X86Operand - Instances of this class represent a parsed X86 machine
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/// instruction.
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struct X86Operand : public MCParsedAsmOperand {
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enum KindTy {
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Token,
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Register,
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Immediate,
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Memory
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} Kind;
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SMLoc StartLoc, EndLoc;
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union {
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struct {
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const char *Data;
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unsigned Length;
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} Tok;
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struct {
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unsigned RegNo;
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} Reg;
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struct {
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const MCExpr *Val;
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} Imm;
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struct {
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unsigned SegReg;
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const MCExpr *Disp;
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unsigned BaseReg;
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unsigned IndexReg;
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unsigned Scale;
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} Mem;
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};
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X86Operand(KindTy K, SMLoc Start, SMLoc End)
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: Kind(K), StartLoc(Start), EndLoc(End) {}
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const { return EndLoc; }
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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unsigned getReg() const {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNo;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getMemDisp() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Disp;
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}
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unsigned getMemSegReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.SegReg;
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}
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unsigned getMemBaseReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.BaseReg;
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}
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unsigned getMemIndexReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg;
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}
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unsigned getMemScale() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Scale;
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}
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bool isToken() const {return Kind == Token; }
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bool isImm() const { return Kind == Immediate; }
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bool isImmSExt8() const {
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// Accept immediates which fit in 8 bits when sign extended, and
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// non-absolute immediates.
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if (!isImm())
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return false;
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if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm())) {
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int64_t Value = CE->getValue();
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return Value == (int64_t) (int8_t) Value;
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}
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return true;
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}
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bool isMem() const { return Kind == Memory; }
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bool isAbsMem() const {
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return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
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!getMemIndexReg() && !getMemScale();
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}
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bool isNoSegMem() const {
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return Kind == Memory && !getMemSegReg();
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}
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bool isReg() const { return Kind == Register; }
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void addRegOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getReg()));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateExpr(getImm()));
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}
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void addImmSExt8Operands(MCInst &Inst, unsigned N) const {
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// FIXME: Support user customization of the render method.
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assert(N == 1 && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateExpr(getImm()));
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}
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void addMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 5) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::CreateImm(getMemScale()));
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Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
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Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
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Inst.addOperand(MCOperand::CreateReg(getMemSegReg()));
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}
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void addAbsMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 1) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
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}
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void addNoSegMemOperands(MCInst &Inst, unsigned N) const {
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assert((N == 4) && "Invalid number of operands!");
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Inst.addOperand(MCOperand::CreateReg(getMemBaseReg()));
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Inst.addOperand(MCOperand::CreateImm(getMemScale()));
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Inst.addOperand(MCOperand::CreateReg(getMemIndexReg()));
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Inst.addOperand(MCOperand::CreateExpr(getMemDisp()));
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}
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static X86Operand *CreateToken(StringRef Str, SMLoc Loc) {
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X86Operand *Res = new X86Operand(Token, Loc, Loc);
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Res->Tok.Data = Str.data();
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Res->Tok.Length = Str.size();
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return Res;
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}
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static X86Operand *CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc) {
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X86Operand *Res = new X86Operand(Register, StartLoc, EndLoc);
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Res->Reg.RegNo = RegNo;
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return Res;
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}
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static X86Operand *CreateImm(const MCExpr *Val, SMLoc StartLoc, SMLoc EndLoc){
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X86Operand *Res = new X86Operand(Immediate, StartLoc, EndLoc);
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Res->Imm.Val = Val;
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return Res;
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}
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/// Create an absolute memory operand.
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static X86Operand *CreateMem(const MCExpr *Disp, SMLoc StartLoc,
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SMLoc EndLoc) {
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X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
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Res->Mem.SegReg = 0;
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Res->Mem.Disp = Disp;
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Res->Mem.BaseReg = 0;
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Res->Mem.IndexReg = 0;
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Res->Mem.Scale = 0;
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return Res;
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}
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/// Create a generalized memory operand.
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static X86Operand *CreateMem(unsigned SegReg, const MCExpr *Disp,
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unsigned BaseReg, unsigned IndexReg,
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unsigned Scale, SMLoc StartLoc, SMLoc EndLoc) {
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// We should never just have a displacement, that should be parsed as an
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// absolute memory operand.
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assert((SegReg || BaseReg || IndexReg) && "Invalid memory operand!");
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// The scale should always be one of {1,2,4,8}.
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assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
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"Invalid scale!");
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X86Operand *Res = new X86Operand(Memory, StartLoc, EndLoc);
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Res->Mem.SegReg = SegReg;
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Res->Mem.Disp = Disp;
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Res->Mem.BaseReg = BaseReg;
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Res->Mem.IndexReg = IndexReg;
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Res->Mem.Scale = Scale;
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return Res;
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}
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};
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} // end anonymous namespace.
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bool X86ATTAsmParser::ParseRegister(unsigned &RegNo,
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SMLoc &StartLoc, SMLoc &EndLoc) {
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RegNo = 0;
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const AsmToken &TokPercent = Parser.getTok();
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assert(TokPercent.is(AsmToken::Percent) && "Invalid token kind!");
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StartLoc = TokPercent.getLoc();
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Parser.Lex(); // Eat percent token.
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const AsmToken &Tok = Parser.getTok();
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if (Tok.isNot(AsmToken::Identifier))
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return Error(Tok.getLoc(), "invalid register name");
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// FIXME: Validate register for the current architecture; we have to do
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// validation later, so maybe there is no need for this here.
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RegNo = MatchRegisterName(Tok.getString());
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if (RegNo == 0)
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return Error(Tok.getLoc(), "invalid register name");
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EndLoc = Tok.getLoc();
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Parser.Lex(); // Eat identifier token.
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return false;
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}
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X86Operand *X86ATTAsmParser::ParseOperand() {
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switch (getLexer().getKind()) {
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default:
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return ParseMemOperand();
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case AsmToken::Percent: {
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// FIXME: if a segment register, this could either be just the seg reg, or
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// the start of a memory operand.
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unsigned RegNo;
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SMLoc Start, End;
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if (ParseRegister(RegNo, Start, End)) return 0;
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return X86Operand::CreateReg(RegNo, Start, End);
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}
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case AsmToken::Dollar: {
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// $42 -> immediate.
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SMLoc Start = Parser.getTok().getLoc(), End;
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Parser.Lex();
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const MCExpr *Val;
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if (getParser().ParseExpression(Val, End))
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return 0;
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return X86Operand::CreateImm(Val, Start, End);
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}
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}
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}
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/// ParseMemOperand: segment: disp(basereg, indexreg, scale)
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X86Operand *X86ATTAsmParser::ParseMemOperand() {
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SMLoc MemStart = Parser.getTok().getLoc();
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// FIXME: If SegReg ':' (e.g. %gs:), eat and remember.
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unsigned SegReg = 0;
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// We have to disambiguate a parenthesized expression "(4+5)" from the start
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// of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
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// only way to do this without lookahead is to eat the '(' and see what is
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// after it.
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const MCExpr *Disp = MCConstantExpr::Create(0, getParser().getContext());
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if (getLexer().isNot(AsmToken::LParen)) {
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SMLoc ExprEnd;
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if (getParser().ParseExpression(Disp, ExprEnd)) return 0;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg == 0)
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return X86Operand::CreateMem(Disp, MemStart, ExprEnd);
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return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
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}
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// Eat the '('.
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Parser.Lex();
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} else {
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// Okay, we have a '('. We don't know if this is an expression or not, but
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// so we have to eat the ( to see beyond it.
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SMLoc LParenLoc = Parser.getTok().getLoc();
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Parser.Lex(); // Eat the '('.
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if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
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// Nothing to do here, fall into the code below with the '(' part of the
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// memory operand consumed.
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} else {
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SMLoc ExprEnd;
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// It must be an parenthesized expression, parse it now.
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if (getParser().ParseParenExpression(Disp, ExprEnd))
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return 0;
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// After parsing the base expression we could either have a parenthesized
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// memory address or not. If not, return now. If so, eat the (.
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if (getLexer().isNot(AsmToken::LParen)) {
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// Unless we have a segment register, treat this as an immediate.
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if (SegReg == 0)
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return X86Operand::CreateMem(Disp, LParenLoc, ExprEnd);
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return X86Operand::CreateMem(SegReg, Disp, 0, 0, 1, MemStart, ExprEnd);
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}
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// Eat the '('.
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Parser.Lex();
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}
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}
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// If we reached here, then we just ate the ( of the memory operand. Process
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// the rest of the memory operand.
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unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
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if (getLexer().is(AsmToken::Percent)) {
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SMLoc L;
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if (ParseRegister(BaseReg, L, L)) return 0;
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}
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if (getLexer().is(AsmToken::Comma)) {
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Parser.Lex(); // Eat the comma.
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// Following the comma we should have either an index register, or a scale
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// value. We don't support the later form, but we want to parse it
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// correctly.
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//
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// Not that even though it would be completely consistent to support syntax
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// like "1(%eax,,1)", the assembler doesn't.
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if (getLexer().is(AsmToken::Percent)) {
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SMLoc L;
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if (ParseRegister(IndexReg, L, L)) return 0;
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if (getLexer().isNot(AsmToken::RParen)) {
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// Parse the scale amount:
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// ::= ',' [scale-expression]
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if (getLexer().isNot(AsmToken::Comma)) {
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Error(Parser.getTok().getLoc(),
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"expected comma in scale expression");
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return 0;
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}
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Parser.Lex(); // Eat the comma.
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if (getLexer().isNot(AsmToken::RParen)) {
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SMLoc Loc = Parser.getTok().getLoc();
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int64_t ScaleVal;
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if (getParser().ParseAbsoluteExpression(ScaleVal))
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return 0;
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// Validate the scale amount.
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if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 && ScaleVal != 8){
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Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
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return 0;
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}
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Scale = (unsigned)ScaleVal;
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}
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}
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} else if (getLexer().isNot(AsmToken::RParen)) {
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// Otherwise we have the unsupported form of a scale amount without an
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// index.
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SMLoc Loc = Parser.getTok().getLoc();
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int64_t Value;
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if (getParser().ParseAbsoluteExpression(Value))
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return 0;
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Error(Loc, "cannot have scale factor without index register");
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return 0;
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}
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}
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// Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
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if (getLexer().isNot(AsmToken::RParen)) {
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Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
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return 0;
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}
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SMLoc MemEnd = Parser.getTok().getLoc();
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Parser.Lex(); // Eat the ')'.
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return X86Operand::CreateMem(SegReg, Disp, BaseReg, IndexReg, Scale,
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MemStart, MemEnd);
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}
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bool X86ATTAsmParser::
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ParseInstruction(const StringRef &Name, SMLoc NameLoc,
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SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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Operands.push_back(X86Operand::CreateToken(Name, NameLoc));
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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// Parse '*' modifier.
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if (getLexer().is(AsmToken::Star)) {
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SMLoc Loc = Parser.getTok().getLoc();
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Operands.push_back(X86Operand::CreateToken("*", Loc));
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Parser.Lex(); // Eat the star.
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}
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// Read the first operand.
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if (X86Operand *Op = ParseOperand())
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Operands.push_back(Op);
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else
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return true;
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while (getLexer().is(AsmToken::Comma)) {
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Parser.Lex(); // Eat the comma.
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// Parse and remember the operand.
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if (X86Operand *Op = ParseOperand())
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Operands.push_back(Op);
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else
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return true;
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}
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}
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return false;
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}
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bool X86ATTAsmParser::ParseDirective(AsmToken DirectiveID) {
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StringRef IDVal = DirectiveID.getIdentifier();
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if (IDVal == ".word")
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return ParseDirectiveWord(2, DirectiveID.getLoc());
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return true;
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}
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/// ParseDirectiveWord
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/// ::= .word [ expression (, expression)* ]
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bool X86ATTAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
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if (getLexer().isNot(AsmToken::EndOfStatement)) {
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for (;;) {
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const MCExpr *Value;
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if (getParser().ParseExpression(Value))
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return true;
|
|
|
|
getParser().getStreamer().EmitValue(Value, Size, 0 /*addrspace*/);
|
|
|
|
if (getLexer().is(AsmToken::EndOfStatement))
|
|
break;
|
|
|
|
// FIXME: Improve diagnostic.
|
|
if (getLexer().isNot(AsmToken::Comma))
|
|
return Error(L, "unexpected token in directive");
|
|
Parser.Lex();
|
|
}
|
|
}
|
|
|
|
Parser.Lex();
|
|
return false;
|
|
}
|
|
|
|
extern "C" void LLVMInitializeX86AsmLexer();
|
|
|
|
// Force static initialization.
|
|
extern "C" void LLVMInitializeX86AsmParser() {
|
|
RegisterAsmParser<X86ATTAsmParser> X(TheX86_32Target);
|
|
RegisterAsmParser<X86ATTAsmParser> Y(TheX86_64Target);
|
|
LLVMInitializeX86AsmLexer();
|
|
}
|
|
|
|
#include "X86GenAsmMatcher.inc"
|