mirror of
https://github.com/c64scene-ar/llvm-6502.git
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6f6ca40ef0
Reapply r242500 now that the swift schedmodel includes LDRLIT. This is mostly done to disable the PostRAScheduler which optimizes for instruction latencies which isn't a good fit for out-of-order architectures. This also allows to leave out the itinerary table in swift in favor of the SchedModel ones. This change leads to performance improvements/regressions by as much as 10% in some benchmarks, in fact we loose 0.4% performance over the llvm-testsuite for reasons that appear to be unknown or out of the compilers control. rdar://20803802 documents the investigation of these effects. While it is probably a good idea to perform the same switch for the other ARM out-of-order CPUs, I limited this change to swift as I cannot perform the benchmark verification on the other CPUs. Differential Revision: http://reviews.llvm.org/D10513 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242588 91177308-0d34-0410-b5e6-96231b3b80d8
108 lines
2.5 KiB
LLVM
108 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=thumbv7s-apple-ios7.0 -o - %s | FileCheck %s
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define i32 @test_return(i32* %p, i32 %oldval, i32 %newval) {
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; CHECK-LABEL: test_return:
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; CHECK: dmb ishst
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; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
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; CHECK: ldrex [[LOADED:r[0-9]+]], [r0]
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; CHECK: cmp [[LOADED]], r1
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; CHECK: bne [[FAILED:LBB[0-9]+_[0-9]+]]
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; CHECK: strex [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0]
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; CHECK: cmp [[STATUS]], #0
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; CHECK: bne [[LOOP]]
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; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: dmb ish
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; CHECK: movs r0, #1
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; CHECK: bx lr
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; CHECK: [[FAILED]]:
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; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: dmb ish
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; CHECK: movs r0, #0
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; CHECK: bx lr
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%pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
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%success = extractvalue { i32, i1 } %pair, 1
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%conv = zext i1 %success to i32
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ret i32 %conv
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}
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define i1 @test_return_bool(i8* %value, i8 %oldValue, i8 %newValue) {
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; CHECK-LABEL: test_return_bool:
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; CHECK: dmb ishst
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; CHECK: uxtb [[OLDBYTE:r[0-9]+]], r1
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; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
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; CHECK: ldrexb [[LOADED:r[0-9]+]], [r0]
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; CHECK: cmp [[LOADED]], [[OLDBYTE]]
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; CHECK: bne [[FAIL:LBB[0-9]+_[0-9]+]]
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; CHECK: strexb [[STATUS:r[0-9]+]], {{r[0-9]+}}, [r0]
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; CHECK: cmp [[STATUS]], #0
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; CHECK: bne [[LOOP]]
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; FIXME: this eor is redundant. Need to teach DAG combine that.
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; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: movs [[TMP:r[0-9]+]], #1
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; CHECK: eor r0, [[TMP]], #1
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; CHECK: bx lr
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; CHECK: [[FAIL]]:
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; CHECK: movs [[TMP:r[0-9]+]], #0
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; CHECK: eor r0, [[TMP]], #1
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; CHECK: bx lr
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%pair = cmpxchg i8* %value, i8 %oldValue, i8 %newValue acq_rel monotonic
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%success = extractvalue { i8, i1 } %pair, 1
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%failure = xor i1 %success, 1
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ret i1 %failure
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}
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define void @test_conditional(i32* %p, i32 %oldval, i32 %newval) {
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; CHECK-LABEL: test_conditional:
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; CHECK: dmb ishst
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; CHECK: [[LOOP:LBB[0-9]+_[0-9]+]]:
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; CHECK: ldrex [[LOADED:r[0-9]+]], [r0]
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; CHECK: cmp [[LOADED]], r1
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; CHECK: bne [[FAILED:LBB[0-9]+_[0-9]+]]
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; CHECK: strex [[STATUS:r[0-9]+]], r2, [r0]
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; CHECK: cmp [[STATUS]], #0
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; CHECK: bne [[LOOP]]
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; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: dmb ish
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; CHECK: b.w _bar
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; CHECK: [[FAILED]]:
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; CHECK-NOT: cmp {{r[0-9]+}}, {{r[0-9]+}}
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; CHECK: dmb ish
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; CHECK: b.w _baz
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%pair = cmpxchg i32* %p, i32 %oldval, i32 %newval seq_cst seq_cst
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%success = extractvalue { i32, i1 } %pair, 1
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br i1 %success, label %true, label %false
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true:
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tail call void @bar() #2
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br label %end
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false:
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tail call void @baz() #2
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br label %end
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end:
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ret void
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}
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declare void @bar()
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declare void @baz()
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