llvm-6502

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Misha Brukman 8996f44f7a Fixed ordering of elements in instructions: although the binary instructions

list (rd, rs1, imm), in that order (bit-wise), the actual assembly syntax is
instr rd, imm, rs1, and that is how they are constructed in the instruction
selector. This fixes the discrepancy.

Also fixed some comments along the same lines and fixed page numbers referring
to where instructions are described in the Sparc manual.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6384 91177308-0d34-0410-b5e6-96231b3b80d8

2003-05-28 17:49:29 +00:00

docs

Changed http://tank ... => http://llvm , and removed an extraneous mailto:.

2003-05-26 00:17:49 +00:00

include

Defines a pass-through debugging emitter -- it writes to a file for inspection

2003-05-27 21:46:56 +00:00

lib

Fixed ordering of elements in instructions: although the binary instructions

2003-05-28 17:49:29 +00:00

runtime

Update to match the reality that is now.