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30fc5bbfd1
beneficial cases. See the changes in test/CodeGen/X86/tail-opts.ll and test/CodeGen/ARM/ifcvt2.ll for details. The fix is to change HashEndOfMBB to hash at most one instruction, instead of trying to apply heuristics about when it will be profitable to consider more than one instruction. The regular tail-merging heuristics are already prepared to handle the same cases, and they're more precise. Also, make test/CodeGen/ARM/ifcvt5.ll and test/CodeGen/Thumb2/thumb2-branch.ll slightly more complex so that they continue to test what they're intended to test. And, this eliminates the problem in test/CodeGen/Thumb2/2009-10-15-ITBlockBranch.ll, the testcase from PR5204. Update it accordingly. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102907 91177308-0d34-0410-b5e6-96231b3b80d8
26 lines
535 B
LLVM
26 lines
535 B
LLVM
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
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@x = external global i32* ; <i32**> [#uses=1]
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define void @foo(i32 %a) {
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entry:
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%tmp = load i32** @x ; <i32*> [#uses=1]
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store i32 %a, i32* %tmp
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ret void
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}
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define i32 @t1(i32 %a, i32 %b) {
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; CHECK: t1:
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; CHECK: ldmialt sp!, {r7, pc}
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entry:
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%tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1]
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br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock
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cond_true: ; preds = %entry
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tail call void @foo( i32 %b )
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ret i32 0
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UnifiedReturnBlock: ; preds = %entry
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ret i32 1
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}
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