mirror of
https://github.com/c64scene-ar/llvm-6502.git
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f58cb6d224
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55857 91177308-0d34-0410-b5e6-96231b3b80d8
679 lines
20 KiB
C++
679 lines
20 KiB
C++
//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86-specific support for the FastISel class. Much
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// of the target-specific code is generated by tablegen in the file
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// X86GenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86ISelLowering.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/Instructions.h"
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#include "llvm/DerivedTypes.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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class X86FastISel : public FastISel {
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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public:
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explicit X86FastISel(MachineFunction &mf,
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DenseMap<const Value *, unsigned> &vm,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &bm)
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: FastISel(mf, vm, bm) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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}
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virtual bool TargetSelectInstruction(Instruction *I);
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#include "X86GenFastISel.inc"
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private:
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bool X86FastEmitLoad(MVT VT, unsigned Op0, Value *V, unsigned &RR);
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bool X86FastEmitStore(MVT VT, unsigned Op0, unsigned Op1, Value *V);
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bool X86SelectConstAddr(Value *V, unsigned &Op0);
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bool X86SelectLoad(Instruction *I);
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bool X86SelectStore(Instruction *I);
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bool X86SelectCmp(Instruction *I);
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bool X86SelectZExt(Instruction *I);
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bool X86SelectBranch(Instruction *I);
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bool X86SelectShift(Instruction *I);
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bool X86SelectSelect(Instruction *I);
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unsigned TargetMaterializeConstant(Constant *C, MachineConstantPool* MCP);
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};
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/// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
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/// The address is either pre-computed, i.e. Op0, or a GlobalAddress, i.e. V.
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/// Return true and the result register by reference if it is possible.
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bool X86FastISel::X86FastEmitLoad(MVT VT, unsigned Op0, Value *V,
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unsigned &ResultReg) {
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8rm;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16rm;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::LD_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::LD_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::LD_Fp80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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ResultReg = createResultReg(RC);
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X86AddressMode AM;
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if (Op0)
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// Address is in register.
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AM.Base.Reg = Op0;
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else
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AM.GV = cast<GlobalValue>(V);
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addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
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return true;
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}
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/// X86FastEmitStore - Emit a machine instruction to store a value Op0 of
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/// type VT. The address is either pre-computed, i.e. Op1, or a GlobalAddress,
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/// i.e. V. Return true if it is possible.
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bool
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X86FastISel::X86FastEmitStore(MVT VT, unsigned Op0, unsigned Op1, Value *V) {
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8mr;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16mr;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32mr;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64mr;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSmr;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::ST_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDmr;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::ST_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::ST_FP80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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X86AddressMode AM;
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if (Op1)
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// Address is in register.
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AM.Base.Reg = Op1;
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else
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AM.GV = cast<GlobalValue>(V);
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addFullAddress(BuildMI(MBB, TII.get(Opc)), AM).addReg(Op0);
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return true;
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}
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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///
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bool X86FastISel::X86SelectConstAddr(Value *V,
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unsigned &Op0) {
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// FIXME: Only GlobalAddress for now.
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GlobalValue *GV = dyn_cast<GlobalValue>(V);
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if (!GV)
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return false;
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if (Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
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// Issue load from stub if necessary.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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}
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Op0 = createResultReg(RC);
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X86AddressMode AM;
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AM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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// Prevent loading GV stub multiple times in same MBB.
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LocalValueMap[V] = Op0;
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}
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return true;
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}
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/// X86SelectStore - Select and emit code to implement store instructions.
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bool X86FastISel::X86SelectStore(Instruction* I) {
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MVT VT = MVT::getMVT(I->getOperand(0)->getType());
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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if (VT == MVT::iPTR)
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// Use pointer type.
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VT = TLI.getPointerTy();
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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if (!TLI.isTypeLegal(VT))
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return false;
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unsigned Op0 = getRegForValue(I->getOperand(0));
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if (Op0 == 0)
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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Value *V = I->getOperand(1);
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unsigned Op1 = getRegForValue(V);
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if (Op1 == 0) {
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// Handle constant load address.
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op1))
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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return X86FastEmitStore(VT, Op0, Op1, V);
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}
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/// X86SelectLoad - Select and emit code to implement load instructions.
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///
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bool X86FastISel::X86SelectLoad(Instruction *I) {
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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if (VT == MVT::iPTR)
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// Use pointer type.
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VT = TLI.getPointerTy();
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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if (!TLI.isTypeLegal(VT))
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return false;
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Value *V = I->getOperand(0);
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unsigned Op0 = getRegForValue(V);
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if (Op0 == 0) {
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// Handle constant load address.
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// FIXME: If load type is something we can't handle, this can result in
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// a dead stub load instruction.
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, Op0))
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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unsigned ResultReg = 0;
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if (X86FastEmitLoad(VT, Op0, V, ResultReg)) {
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UpdateValueMap(I, ResultReg);
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return true;
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}
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return false;
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}
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bool X86FastISel::X86SelectCmp(Instruction *I) {
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CmpInst *CI = cast<CmpInst>(I);
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MVT VT = TLI.getValueType(I->getOperand(0)->getType());
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if (!TLI.isTypeLegal(VT))
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return false;
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unsigned Op0Reg = getRegForValue(CI->getOperand(0));
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if (Op0Reg == 0) return false;
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unsigned Op1Reg = getRegForValue(CI->getOperand(1));
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if (Op1Reg == 0) return false;
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unsigned Opc;
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switch (VT.getSimpleVT()) {
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case MVT::i8: Opc = X86::CMP8rr; break;
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case MVT::i16: Opc = X86::CMP16rr; break;
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case MVT::i32: Opc = X86::CMP32rr; break;
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case MVT::i64: Opc = X86::CMP64rr; break;
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case MVT::f32: Opc = X86::UCOMISSrr; break;
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case MVT::f64: Opc = X86::UCOMISDrr; break;
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default: return false;
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}
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unsigned ResultReg = createResultReg(&X86::GR8RegClass);
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switch (CI->getPredicate()) {
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case CmpInst::FCMP_OEQ: {
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unsigned EReg = createResultReg(&X86::GR8RegClass);
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unsigned NPReg = createResultReg(&X86::GR8RegClass);
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETEr), EReg);
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BuildMI(MBB, TII.get(X86::SETNPr), NPReg);
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BuildMI(MBB, TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
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break;
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}
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case CmpInst::FCMP_UNE: {
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unsigned NEReg = createResultReg(&X86::GR8RegClass);
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unsigned PReg = createResultReg(&X86::GR8RegClass);
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETNEr), NEReg);
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BuildMI(MBB, TII.get(X86::SETPr), PReg);
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BuildMI(MBB, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
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break;
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}
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case CmpInst::FCMP_OGT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
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break;
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case CmpInst::FCMP_OGE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
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break;
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case CmpInst::FCMP_OLT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
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break;
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case CmpInst::FCMP_OLE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
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break;
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case CmpInst::FCMP_ONE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
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break;
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case CmpInst::FCMP_ORD:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETNPr), ResultReg);
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break;
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case CmpInst::FCMP_UNO:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETPr), ResultReg);
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break;
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case CmpInst::FCMP_UEQ:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
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break;
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case CmpInst::FCMP_UGT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
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break;
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case CmpInst::FCMP_UGE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op1Reg).addReg(Op0Reg);
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BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
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break;
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case CmpInst::FCMP_ULT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
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break;
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case CmpInst::FCMP_ULE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
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break;
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case CmpInst::ICMP_EQ:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETEr), ResultReg);
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break;
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case CmpInst::ICMP_NE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETNEr), ResultReg);
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break;
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case CmpInst::ICMP_UGT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETAr), ResultReg);
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break;
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case CmpInst::ICMP_UGE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETAEr), ResultReg);
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break;
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case CmpInst::ICMP_ULT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETBr), ResultReg);
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break;
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case CmpInst::ICMP_ULE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETBEr), ResultReg);
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break;
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case CmpInst::ICMP_SGT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETGr), ResultReg);
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break;
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case CmpInst::ICMP_SGE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETGEr), ResultReg);
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break;
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case CmpInst::ICMP_SLT:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETLr), ResultReg);
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break;
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case CmpInst::ICMP_SLE:
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BuildMI(MBB, TII.get(Opc)).addReg(Op0Reg).addReg(Op1Reg);
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BuildMI(MBB, TII.get(X86::SETLEr), ResultReg);
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break;
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default:
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return false;
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}
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UpdateValueMap(I, ResultReg);
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return true;
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}
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bool X86FastISel::X86SelectZExt(Instruction *I) {
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// Special-case hack: The only i1 values we know how to produce currently
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// set the upper bits of an i8 value to zero.
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if (I->getType() == Type::Int8Ty &&
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I->getOperand(0)->getType() == Type::Int1Ty) {
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unsigned ResultReg = getRegForValue(I->getOperand(0));
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if (ResultReg == 0) return false;
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UpdateValueMap(I, ResultReg);
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return true;
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}
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return false;
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}
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bool X86FastISel::X86SelectBranch(Instruction *I) {
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BranchInst *BI = cast<BranchInst>(I);
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|
// Unconditional branches are selected by tablegen-generated code.
|
|
unsigned OpReg = getRegForValue(BI->getCondition());
|
|
if (OpReg == 0) return false;
|
|
MachineBasicBlock *TrueMBB = MBBMap[BI->getSuccessor(0)];
|
|
MachineBasicBlock *FalseMBB = MBBMap[BI->getSuccessor(1)];
|
|
|
|
BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
|
|
BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
|
|
BuildMI(MBB, TII.get(X86::JMP)).addMBB(FalseMBB);
|
|
|
|
MBB->addSuccessor(TrueMBB);
|
|
MBB->addSuccessor(FalseMBB);
|
|
|
|
return true;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectShift(Instruction *I) {
|
|
unsigned CReg = 0;
|
|
unsigned Opc = 0;
|
|
const TargetRegisterClass *RC = NULL;
|
|
if (I->getType() == Type::Int8Ty) {
|
|
CReg = X86::CL;
|
|
RC = &X86::GR8RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR8rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR8rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL8rCL; break;
|
|
default: return false;
|
|
}
|
|
} else if (I->getType() == Type::Int16Ty) {
|
|
CReg = X86::CX;
|
|
RC = &X86::GR16RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR16rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR16rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL16rCL; break;
|
|
default: return false;
|
|
}
|
|
} else if (I->getType() == Type::Int32Ty) {
|
|
CReg = X86::ECX;
|
|
RC = &X86::GR32RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR32rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR32rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL32rCL; break;
|
|
default: return false;
|
|
}
|
|
} else if (I->getType() == Type::Int64Ty) {
|
|
CReg = X86::RCX;
|
|
RC = &X86::GR64RegClass;
|
|
switch (I->getOpcode()) {
|
|
case Instruction::LShr: Opc = X86::SHR64rCL; break;
|
|
case Instruction::AShr: Opc = X86::SAR64rCL; break;
|
|
case Instruction::Shl: Opc = X86::SHL64rCL; break;
|
|
default: return false;
|
|
}
|
|
} else {
|
|
return false;
|
|
}
|
|
|
|
MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
|
|
if (VT == MVT::Other || !TLI.isTypeLegal(VT))
|
|
return false;
|
|
|
|
unsigned Op0Reg = getRegForValue(I->getOperand(0));
|
|
if (Op0Reg == 0) return false;
|
|
unsigned Op1Reg = getRegForValue(I->getOperand(1));
|
|
if (Op1Reg == 0) return false;
|
|
TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC);
|
|
unsigned ResultReg = createResultReg(RC);
|
|
BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op0Reg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool X86FastISel::X86SelectSelect(Instruction *I) {
|
|
const Type *Ty = I->getType();
|
|
if (isa<PointerType>(Ty))
|
|
Ty = TLI.getTargetData()->getIntPtrType();
|
|
|
|
unsigned Opc = 0;
|
|
const TargetRegisterClass *RC = NULL;
|
|
if (Ty == Type::Int16Ty) {
|
|
Opc = X86::CMOVE16rr;
|
|
RC = &X86::GR16RegClass;
|
|
} else if (Ty == Type::Int32Ty) {
|
|
Opc = X86::CMOVE32rr;
|
|
RC = &X86::GR32RegClass;
|
|
} else if (Ty == Type::Int64Ty) {
|
|
Opc = X86::CMOVE64rr;
|
|
RC = &X86::GR64RegClass;
|
|
} else {
|
|
return false;
|
|
}
|
|
|
|
MVT VT = MVT::getMVT(Ty, /*HandleUnknown=*/true);
|
|
if (VT == MVT::Other || !TLI.isTypeLegal(VT))
|
|
return false;
|
|
|
|
unsigned Op0Reg = getRegForValue(I->getOperand(0));
|
|
if (Op0Reg == 0) return false;
|
|
unsigned Op1Reg = getRegForValue(I->getOperand(1));
|
|
if (Op1Reg == 0) return false;
|
|
unsigned Op2Reg = getRegForValue(I->getOperand(2));
|
|
if (Op2Reg == 0) return false;
|
|
|
|
BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
|
|
unsigned ResultReg = createResultReg(RC);
|
|
BuildMI(MBB, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
|
|
UpdateValueMap(I, ResultReg);
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
X86FastISel::TargetSelectInstruction(Instruction *I) {
|
|
switch (I->getOpcode()) {
|
|
default: break;
|
|
case Instruction::Load:
|
|
return X86SelectLoad(I);
|
|
case Instruction::Store:
|
|
return X86SelectStore(I);
|
|
case Instruction::ICmp:
|
|
case Instruction::FCmp:
|
|
return X86SelectCmp(I);
|
|
case Instruction::ZExt:
|
|
return X86SelectZExt(I);
|
|
case Instruction::Br:
|
|
return X86SelectBranch(I);
|
|
case Instruction::LShr:
|
|
case Instruction::AShr:
|
|
case Instruction::Shl:
|
|
return X86SelectShift(I);
|
|
case Instruction::Select:
|
|
return X86SelectSelect(I);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
unsigned X86FastISel::TargetMaterializeConstant(Constant *C,
|
|
MachineConstantPool* MCP) {
|
|
unsigned CPLoad = getRegForValue(C);
|
|
if (CPLoad != 0)
|
|
return CPLoad;
|
|
|
|
// Can't handle PIC-mode yet.
|
|
if (TM.getRelocationModel() == Reloc::PIC_)
|
|
return 0;
|
|
|
|
MVT VT = MVT::getMVT(C->getType(), /*HandleUnknown=*/true);
|
|
if (VT == MVT::Other || !VT.isSimple())
|
|
// Unhandled type. Halt "fast" selection and bail.
|
|
return false;
|
|
if (VT == MVT::iPTR)
|
|
// Use pointer type.
|
|
VT = TLI.getPointerTy();
|
|
// We only handle legal types. For example, on x86-32 the instruction
|
|
// selector contains all of the 64-bit instructions from x86-64,
|
|
// under the assumption that i64 won't be used if the target doesn't
|
|
// support it.
|
|
if (!TLI.isTypeLegal(VT))
|
|
return false;
|
|
|
|
// Get opcode and regclass of the output for the given load instruction.
|
|
unsigned Opc = 0;
|
|
const TargetRegisterClass *RC = NULL;
|
|
switch (VT.getSimpleVT()) {
|
|
default: return false;
|
|
case MVT::i8:
|
|
Opc = X86::MOV8rm;
|
|
RC = X86::GR8RegisterClass;
|
|
break;
|
|
case MVT::i16:
|
|
Opc = X86::MOV16rm;
|
|
RC = X86::GR16RegisterClass;
|
|
break;
|
|
case MVT::i32:
|
|
Opc = X86::MOV32rm;
|
|
RC = X86::GR32RegisterClass;
|
|
break;
|
|
case MVT::i64:
|
|
// Must be in x86-64 mode.
|
|
Opc = X86::MOV64rm;
|
|
RC = X86::GR64RegisterClass;
|
|
break;
|
|
case MVT::f32:
|
|
if (Subtarget->hasSSE1()) {
|
|
Opc = X86::MOVSSrm;
|
|
RC = X86::FR32RegisterClass;
|
|
} else {
|
|
Opc = X86::LD_Fp32m;
|
|
RC = X86::RFP32RegisterClass;
|
|
}
|
|
break;
|
|
case MVT::f64:
|
|
if (Subtarget->hasSSE2()) {
|
|
Opc = X86::MOVSDrm;
|
|
RC = X86::FR64RegisterClass;
|
|
} else {
|
|
Opc = X86::LD_Fp64m;
|
|
RC = X86::RFP64RegisterClass;
|
|
}
|
|
break;
|
|
case MVT::f80:
|
|
Opc = X86::LD_Fp80m;
|
|
RC = X86::RFP80RegisterClass;
|
|
break;
|
|
}
|
|
|
|
unsigned ResultReg = createResultReg(RC);
|
|
if (isa<GlobalValue>(C)) {
|
|
// FIXME: If store value type is something we can't handle, this can result
|
|
// in a dead stub load instruction.
|
|
if (X86SelectConstAddr(C, ResultReg))
|
|
return ResultReg;
|
|
return 0;
|
|
}
|
|
|
|
|
|
unsigned MCPOffset = MCP->getConstantPoolIndex(C, 0);
|
|
addConstantPoolReference(BuildMI(MBB, TII.get(Opc), ResultReg), MCPOffset);
|
|
UpdateValueMap(C, ResultReg);
|
|
return ResultReg;
|
|
}
|
|
|
|
namespace llvm {
|
|
llvm::FastISel *X86::createFastISel(MachineFunction &mf,
|
|
DenseMap<const Value *, unsigned> &vm,
|
|
DenseMap<const BasicBlock *, MachineBasicBlock *> &bm) {
|
|
return new X86FastISel(mf, vm, bm);
|
|
}
|
|
}
|