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914f2ff9e6
InlineSpiller inserts loads and spills immediately instead of deferring to VirtRegMap. This is possible now because SlotIndexes allows instructions to be inserted and renumbered. This is work in progress, and is mostly a copy of TrivialSpiller so far. It works very well for functions that don't require spilling. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107227 91177308-0d34-0410-b5e6-96231b3b80d8
137 lines
4.8 KiB
C++
137 lines
4.8 KiB
C++
//===-------- InlineSpiller.cpp - Insert spills and restores inline -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The inline spiller modifies the machine function directly instead of
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// inserting spills and restores in VirtRegMap.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "spiller"
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#include "Spiller.h"
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#include "VirtRegMap.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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namespace {
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class InlineSpiller : public Spiller {
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MachineFunction &mf_;
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LiveIntervals &lis_;
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VirtRegMap &vrm_;
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MachineFrameInfo &mfi_;
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MachineRegisterInfo &mri_;
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const TargetInstrInfo &tii_;
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const TargetRegisterInfo &tri_;
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~InlineSpiller() {}
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public:
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InlineSpiller(MachineFunction *mf, LiveIntervals *lis, VirtRegMap *vrm)
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: mf_(*mf), lis_(*lis), vrm_(*vrm),
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mfi_(*mf->getFrameInfo()),
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mri_(mf->getRegInfo()),
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tii_(*mf->getTarget().getInstrInfo()),
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tri_(*mf->getTarget().getRegisterInfo()) {}
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void spill(LiveInterval *li,
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std::vector<LiveInterval*> &newIntervals,
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SmallVectorImpl<LiveInterval*> &spillIs,
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SlotIndex *earliestIndex);
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};
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}
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namespace llvm {
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Spiller *createInlineSpiller(MachineFunction *mf,
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LiveIntervals *lis,
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const MachineLoopInfo *mli,
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VirtRegMap *vrm) {
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return new InlineSpiller(mf, lis, vrm);
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}
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}
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void InlineSpiller::spill(LiveInterval *li,
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std::vector<LiveInterval*> &newIntervals,
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SmallVectorImpl<LiveInterval*> &spillIs,
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SlotIndex *earliestIndex) {
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DEBUG(dbgs() << "Inline spilling " << *li << "\n");
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assert(li->isSpillable() && "Attempting to spill already spilled value.");
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assert(!li->isStackSlot() && "Trying to spill a stack slot.");
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const TargetRegisterClass *RC = mri_.getRegClass(li->reg);
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unsigned SS = vrm_.assignVirt2StackSlot(li->reg);
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for (MachineRegisterInfo::reg_iterator RI = mri_.reg_begin(li->reg);
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MachineInstr *MI = RI.skipInstruction();) {
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SlotIndex Idx = lis_.getInstructionIndex(MI).getDefIndex();
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// Analyze instruction.
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bool Reads, Writes;
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SmallVector<unsigned, 8> Ops;
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tie(Reads, Writes) = MI->readsWritesVirtualRegister(li->reg, &Ops);
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// Allocate interval around instruction.
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// FIXME: Infer regclass from instruction alone.
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unsigned NewVReg = mri_.createVirtualRegister(RC);
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vrm_.grow();
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LiveInterval &NewLI = lis_.getOrCreateInterval(NewVReg);
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NewLI.markNotSpillable();
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// Reload if instruction reads register.
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if (Reads) {
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MachineBasicBlock::iterator MII = MI;
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tii_.loadRegFromStackSlot(*MI->getParent(), MII, NewVReg, SS, RC, &tri_);
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--MII; // Point to load instruction.
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SlotIndex LoadIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
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DEBUG(dbgs() << "\treload: " << LoadIdx << '\t' << *MII);
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VNInfo *LoadVNI = NewLI.getNextValue(LoadIdx, 0, true,
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lis_.getVNInfoAllocator());
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NewLI.addRange(LiveRange(LoadIdx, Idx, LoadVNI));
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}
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// Rewrite instruction operands.
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bool hasLiveDef = false;
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for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
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MachineOperand &MO = MI->getOperand(Ops[i]);
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MO.setReg(NewVReg);
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if (MO.isUse()) {
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if (!MI->isRegTiedToDefOperand(Ops[i]))
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MO.setIsKill();
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} else {
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if (!MO.isDead())
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hasLiveDef = true;
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}
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}
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DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI);
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// Spill is instruction writes register.
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// FIXME: Use a second vreg if instruction has no tied ops.
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if (Writes && hasLiveDef) {
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MachineBasicBlock::iterator MII = MI;
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tii_.storeRegToStackSlot(*MI->getParent(), ++MII, NewVReg, true, SS, RC,
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&tri_);
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--MII; // Point to store instruction.
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SlotIndex StoreIdx = lis_.InsertMachineInstrInMaps(MII).getDefIndex();
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DEBUG(dbgs() << "\tspilled: " << StoreIdx << '\t' << *MII);
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VNInfo *StoreVNI = NewLI.getNextValue(Idx, 0, true,
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lis_.getVNInfoAllocator());
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NewLI.addRange(LiveRange(Idx, StoreIdx, StoreVNI));
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}
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DEBUG(dbgs() << "\tinterval: " << NewLI << '\n');
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newIntervals.push_back(&NewLI);
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}
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}
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