llvm-6502/test/CodeGen
Matt Arsenault 8a44761afe R600/SI: Implement correct f64 fdiv
This version passes the OpenCL conformance test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229239 91177308-0d34-0410-b5e6-96231b3b80d8
2015-02-14 04:30:08 +00:00
..
AArch64 [SimplifyCFG] Be more aggressive 2015-02-13 10:48:30 +00:00
ARM [SimplifyCFG] Swap to using TargetTransformInfo for cost 2015-02-11 12:15:41 +00:00
BPF
CPP
Generic
Hexagon
Inputs
Mips [mips][microMIPS] Delay slot filler: Replace the microMIPS JR with the JRC 2015-02-13 17:51:27 +00:00
MSP430
NVPTX
PowerPC [CodeGenPrepare] Removed duplicate logic. SimplifyCFG already knows how to speculate calls to cttz/ctlz. 2015-02-13 14:15:48 +00:00
R600 R600/SI: Implement correct f64 fdiv 2015-02-14 04:30:08 +00:00
SPARC
SystemZ
Thumb
Thumb2 Make buildbots better. 2015-02-11 12:24:09 +00:00
X86 Revert "On ELF, put PIC jump tables in a non executable section." 2015-02-14 01:16:54 +00:00
XCore