David Majnemer 8a55c2ecd4 X86: Bad peephole interaction between adc, MOV32r0 ... The peephole tries to reorder MOV32r0 instructions such that they are before the instruction that modifies EFLAGS. The problem is that the peephole does not consider the case where the instruction that modifies EFLAGS also depends on the previous state of EFLAGS. Instead, walk backwards until we find an instruction that has a def for EFLAGS but does not have a use. If we find such an instruction, insert the MOV32r0 before it. If it cannot find such an instruction, skip the optimization. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182184 91177308-0d34-0410-b5e6-96231b3b80d8		2013-05-18 01:02:03 +00:00
..
AArch64	More test coverage for addFrameMove.	2013-05-16 20:50:56 +00:00
ARM	Support unaligned load/store on more ARM targets	2013-05-17 23:49:01 +00:00
CPP	test commit: remove blank line.	2013-03-14 05:43:59 +00:00
Generic	TBAA: remove !tbaa from testing cases if not used.	2013-04-30 17:52:57 +00:00
Hexagon	Hexagon: Pass to replace tranfer/copy instructions into combine instruction	2013-05-14 18:54:06 +00:00
Inputs	Revert "Adding DIImportedModules to DIScopes."	2013-03-28 02:44:59 +00:00
MBlaze	Remove unnecessary leading comment characters in lit-only file	2013-03-18 22:08:16 +00:00
Mips	[mips] Improve instruction selection for pattern (store (fp_to_sint $src), $ptr).	2013-05-16 21:17:15 +00:00
MSP430	DAGCombiner: Simplify inverted bit tests	2013-05-08 06:44:42 +00:00
NVPTX	[NVPTX] Remove support for SM < 2.0. This was never fully supported anyway.	2013-03-30 14:29:30 +00:00
PowerPC	Fix cpu on test CodeGen/PowerPC/ctrloop-fp64.ll	2013-05-16 20:28:05 +00:00
R600	R600: Lower int_load_input to copyFromReg instead of Register node	2013-05-17 16:51:06 +00:00
SI
SPARC	[Sparc] Implements hasReservedCallFrame and hasFP.	2013-05-17 15:14:34 +00:00
SystemZ	[SystemZ] Make use of SUBTRACT HALFWORD	2013-05-15 15:05:29 +00:00
Thumb	LocalStackSlotAllocation improvements	2013-04-30 20:04:37 +00:00
Thumb2	Fix ARM FastISel tests, as a first step to enabling ARM FastISel	2013-05-14 16:26:38 +00:00
X86	X86: Bad peephole interaction between adc, MOV32r0	2013-05-18 01:02:03 +00:00
XCore	[XCore] Fix handling of functions where only the LR is spilled.	2013-05-09 16:43:42 +00:00