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Improved the AnalyzeBranch, InsertBranch, and RemoveBranch functions in order to handle more of our branch instructions. This requires changes to analyzeCompare and PredicateInstructions. Specifically, we've added support for new value compare jumps, improved handling of endloop, added more compare instructions, and improved support for predicate instructions. Differential Revision: http://reviews.llvm.org/D9559 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@236876 91177308-0d34-0410-b5e6-96231b3b80d8
235 lines
10 KiB
C++
235 lines
10 KiB
C++
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//===- HexagonInstrInfo.h - Hexagon Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Hexagon implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
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#define LLVM_LIB_TARGET_HEXAGON_HEXAGONINSTRINFO_H
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#include "HexagonRegisterInfo.h"
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#include "MCTargetDesc/HexagonBaseInfo.h"
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#include "llvm/CodeGen/MachineBranchProbabilityInfo.h"
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#include "llvm/Target/TargetFrameLowering.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#define GET_INSTRINFO_HEADER
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#include "HexagonGenInstrInfo.inc"
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namespace llvm {
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struct EVT;
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class HexagonSubtarget;
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class HexagonInstrInfo : public HexagonGenInstrInfo {
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virtual void anchor();
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const HexagonRegisterInfo RI;
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const HexagonSubtarget &Subtarget;
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public:
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typedef unsigned Opcode_t;
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explicit HexagonInstrInfo(HexagonSubtarget &ST);
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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const HexagonRegisterInfo &getRegisterInfo() const { return RI; }
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/// isLoadFromStackSlot - If the specified machine instruction is a direct
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/// load from a stack slot, return the virtual or physical register number of
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/// the destination along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than loading from the stack slot.
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unsigned isLoadFromStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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/// isStoreToStackSlot - If the specified machine instruction is a direct
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/// store to a stack slot, return the virtual or physical register number of
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/// the source reg along with the FrameIndex of the loaded stack slot. If
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/// not, return 0. This predicate must return 0 if the instruction has
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/// any side effects other than storing to the stack slot.
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unsigned isStoreToStackSlot(const MachineInstr *MI,
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int &FrameIndex) const override;
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bool AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
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MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond,
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bool AllowModify) const override;
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unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
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unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
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MachineBasicBlock *FBB,
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const SmallVectorImpl<MachineOperand> &Cond,
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DebugLoc DL) const override;
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bool analyzeCompare(const MachineInstr *MI,
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unsigned &SrcReg, unsigned &SrcReg2,
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int &Mask, int &Value) const override;
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void copyPhysReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg,
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bool KillSrc) const override;
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void storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, bool isKill, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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void loadRegFromStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
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const TargetRegisterClass *RC,
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const TargetRegisterInfo *TRI) const override;
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void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
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SmallVectorImpl<MachineOperand> &Addr,
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const TargetRegisterClass *RC,
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SmallVectorImpl<MachineInstr*> &NewMIs) const;
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/// expandPostRAPseudo - This function is called for all pseudo instructions
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/// that remain after register allocation. Many pseudo instructions are
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/// created to help register allocation. This is the place to convert them
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/// into real instructions. The target can edit MI in place, or it can insert
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/// new instructions and erase MI. The function should return true if
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/// anything was changed.
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bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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ArrayRef<unsigned> Ops,
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int FrameIndex) const override;
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MachineInstr *foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
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ArrayRef<unsigned> Ops,
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MachineInstr *LoadMI) const override {
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return nullptr;
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}
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unsigned createVR(MachineFunction* MF, MVT VT) const;
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bool isBranch(const MachineInstr *MI) const;
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bool isPredicable(MachineInstr *MI) const override;
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bool PredicateInstruction(MachineInstr *MI,
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const SmallVectorImpl<MachineOperand> &Cond) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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unsigned ExtraPredCycles,
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const BranchProbability &Probability) const override;
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bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
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unsigned NumTCycles, unsigned ExtraTCycles,
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MachineBasicBlock &FMBB,
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unsigned NumFCycles, unsigned ExtraFCycles,
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const BranchProbability &Probability) const override;
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bool isPredicated(const MachineInstr *MI) const override;
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bool isPredicated(unsigned Opcode) const;
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bool isPredicatedTrue(const MachineInstr *MI) const;
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bool isPredicatedTrue(unsigned Opcode) const;
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bool isPredicatedNew(const MachineInstr *MI) const;
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bool isPredicatedNew(unsigned Opcode) const;
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bool DefinesPredicate(MachineInstr *MI,
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std::vector<MachineOperand> &Pred) const override;
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bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
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const SmallVectorImpl<MachineOperand> &Pred2) const override;
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bool
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ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
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bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
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const BranchProbability &Probability) const override;
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DFAPacketizer *
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CreateTargetScheduleState(const TargetSubtargetInfo &STI) const override;
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bool isSchedulingBoundary(const MachineInstr *MI,
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const MachineBasicBlock *MBB,
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const MachineFunction &MF) const override;
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bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
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bool isValidAutoIncImm(const EVT VT, const int Offset) const;
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bool isMemOp(const MachineInstr *MI) const;
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bool isSpillPredRegOp(const MachineInstr *MI) const;
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bool isU6_3Immediate(const int value) const;
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bool isU6_2Immediate(const int value) const;
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bool isU6_1Immediate(const int value) const;
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bool isU6_0Immediate(const int value) const;
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bool isS4_3Immediate(const int value) const;
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bool isS4_2Immediate(const int value) const;
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bool isS4_1Immediate(const int value) const;
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bool isS4_0Immediate(const int value) const;
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bool isS12_Immediate(const int value) const;
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bool isU6_Immediate(const int value) const;
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bool isS8_Immediate(const int value) const;
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bool isS6_Immediate(const int value) const;
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bool isSaveCalleeSavedRegsCall(const MachineInstr* MI) const;
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bool isConditionalTransfer(const MachineInstr* MI) const;
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bool isConditionalALU32 (const MachineInstr* MI) const;
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bool isConditionalLoad (const MachineInstr* MI) const;
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bool isConditionalStore(const MachineInstr* MI) const;
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bool isNewValueInst(const MachineInstr* MI) const;
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bool isNewValue(const MachineInstr* MI) const;
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bool isNewValue(Opcode_t Opcode) const;
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bool isDotNewInst(const MachineInstr* MI) const;
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int GetDotOldOp(const int opc) const;
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int GetDotNewOp(const MachineInstr* MI) const;
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int GetDotNewPredOp(MachineInstr *MI,
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const MachineBranchProbabilityInfo
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*MBPI) const;
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bool mayBeNewStore(const MachineInstr* MI) const;
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bool isDeallocRet(const MachineInstr *MI) const;
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unsigned getInvertedPredicatedOpcode(const int Opc) const;
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bool isExtendable(const MachineInstr* MI) const;
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bool isExtended(const MachineInstr* MI) const;
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bool isPostIncrement(const MachineInstr* MI) const;
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bool isNewValueStore(const MachineInstr* MI) const;
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bool isNewValueStore(unsigned Opcode) const;
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bool isNewValueJump(const MachineInstr* MI) const;
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bool isNewValueJump(Opcode_t Opcode) const;
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bool isNewValueJumpCandidate(const MachineInstr *MI) const;
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void immediateExtend(MachineInstr *MI) const;
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bool isConstExtended(const MachineInstr *MI) const;
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unsigned getSize(const MachineInstr *MI) const;
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int getDotNewPredJumpOp(MachineInstr *MI,
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const MachineBranchProbabilityInfo *MBPI) const;
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unsigned getAddrMode(const MachineInstr* MI) const;
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bool isOperandExtended(const MachineInstr *MI,
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unsigned short OperandNum) const;
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unsigned short getCExtOpNum(const MachineInstr *MI) const;
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int getMinValue(const MachineInstr *MI) const;
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int getMaxValue(const MachineInstr *MI) const;
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bool NonExtEquivalentExists (const MachineInstr *MI) const;
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short getNonExtOpcode(const MachineInstr *MI) const;
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bool PredOpcodeHasJMP_c(Opcode_t Opcode) const;
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bool predOpcodeHasNot(const SmallVectorImpl<MachineOperand> &Cond) const;
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bool isEndLoopN(Opcode_t Opcode) const;
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bool getPredReg(const SmallVectorImpl<MachineOperand> &Cond,
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unsigned &PredReg, unsigned &PredRegPos,
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unsigned &PredRegFlags) const;
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int getCondOpcode(int Opc, bool sense) const;
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};
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}
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#endif
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