Andrea Di Biagio 8a712ba229 [X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 (and vice versa). ... Before this patch, the backend always emitted a store+load sequence to bitconvert from f64 to i64 the input operand of a ISD::BITCAST dag node that performed a bitconvert from type MVT::f64 to type MVT::v2i32. The resulting i64 node was then used to build a v2i32 vector. With this patch, the backend now produces a cheaper SCALAR_TO_VECTOR from MVT::f64 to MVT::v2f64. That SCALAR_TO_VECTOR is then followed by a "free" bitcast to type MVT::v4i32. The elements of the resulting v4i32 are then extracted to build a v2i32 vector (which is illegal and therefore promoted to MVT::v2i64). This is in general cheaper than emitting a stack store+load sequence to bitconvert the operand from type f64 to type i64. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208107 91177308-0d34-0410-b5e6-96231b3b80d8		2014-05-06 17:09:03 +00:00
..
AArch64	Implememting named register intrinsics	2014-05-06 16:51:25 +00:00
ARM	Implememting named register intrinsics	2014-05-06 16:51:25 +00:00
ARM64	Implememting named register intrinsics	2014-05-06 16:51:25 +00:00
CPP
Generic	MC: move test from Generic to COFF	2014-04-23 21:41:07 +00:00
Hexagon
Inputs
Mips	Add basic functionality for assignment of ints.	2014-05-01 20:39:21 +00:00
MSP430
NVPTX
PowerPC
R600	R600: Expand i64 ISD:SUB	2014-05-05 21:47:15 +00:00
SPARC	Remove the -disable-cfi option.	2014-05-05 17:33:26 +00:00
SystemZ
Thumb
Thumb2
X86	[X86] Improve the lowering of BITCAST dag nodes from type f64 to type v2i32 (and vice versa).	2014-05-06 17:09:03 +00:00
XCore