mirror of
https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26742 91177308-0d34-0410-b5e6-96231b3b80d8
850 lines
28 KiB
C++
850 lines
28 KiB
C++
//===- X86ISelDAGToDAG.cpp - A DAG pattern matching inst selector for X86 -===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the Evan Cheng and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines a DAG pattern matching instruction selector for X86,
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// converting from a legalized dag to a X86 dag.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "isel"
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86ISelLowering.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/GlobalValue.h"
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#include "llvm/Instructions.h"
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#include "llvm/Support/CFG.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/ADT/Statistic.h"
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#include <iostream>
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#include <set>
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using namespace llvm;
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//===----------------------------------------------------------------------===//
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// Pattern Matcher Implementation
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//===----------------------------------------------------------------------===//
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namespace {
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/// X86ISelAddressMode - This corresponds to X86AddressMode, but uses
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/// SDOperand's instead of register numbers for the leaves of the matched
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/// tree.
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struct X86ISelAddressMode {
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enum {
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RegBase,
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FrameIndexBase,
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} BaseType;
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struct { // This is really a union, discriminated by BaseType!
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SDOperand Reg;
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int FrameIndex;
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} Base;
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unsigned Scale;
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SDOperand IndexReg;
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unsigned Disp;
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GlobalValue *GV;
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Constant *CP;
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unsigned Align; // CP alignment.
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X86ISelAddressMode()
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: BaseType(RegBase), Scale(1), IndexReg(), Disp(0), GV(0),
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CP(0), Align(0) {
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}
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};
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}
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namespace {
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Statistic<>
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NumFPKill("x86-codegen", "Number of FP_REG_KILL instructions added");
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//===--------------------------------------------------------------------===//
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/// ISel - X86 specific code to select X86 machine instructions for
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/// SelectionDAG operations.
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///
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class X86DAGToDAGISel : public SelectionDAGISel {
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/// ContainsFPCode - Every instruction we select that uses or defines a FP
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/// register should set this to true.
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bool ContainsFPCode;
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/// X86Lowering - This object fully describes how to lower LLVM code to an
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/// X86-specific SelectionDAG.
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X86TargetLowering X86Lowering;
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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unsigned GlobalBaseReg;
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public:
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X86DAGToDAGISel(X86TargetMachine &TM)
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: SelectionDAGISel(X86Lowering),
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X86Lowering(*TM.getTargetLowering()) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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}
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virtual bool runOnFunction(Function &Fn) {
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// Make sure we re-emit a set of the global base reg if necessary
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GlobalBaseReg = 0;
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return SelectionDAGISel::runOnFunction(Fn);
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}
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virtual const char *getPassName() const {
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return "X86 DAG->DAG Instruction Selection";
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}
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/// InstructionSelectBasicBlock - This callback is invoked by
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/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
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virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
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virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
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// Include the pieces autogenerated from the target description.
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#include "X86GenDAGISel.inc"
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private:
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void Select(SDOperand &Result, SDOperand N);
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bool MatchAddress(SDOperand N, X86ISelAddressMode &AM, bool isRoot = true);
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bool SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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bool SelectLEAAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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bool TryFoldLoad(SDOperand P, SDOperand N,
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SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp);
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inline void getAddressOperands(X86ISelAddressMode &AM, SDOperand &Base,
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SDOperand &Scale, SDOperand &Index,
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SDOperand &Disp) {
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Base = (AM.BaseType == X86ISelAddressMode::FrameIndexBase) ?
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CurDAG->getTargetFrameIndex(AM.Base.FrameIndex, MVT::i32) : AM.Base.Reg;
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Scale = getI8Imm(AM.Scale);
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Index = AM.IndexReg;
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Disp = AM.GV ? CurDAG->getTargetGlobalAddress(AM.GV, MVT::i32, AM.Disp)
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: (AM.CP ?
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CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Align, AM.Disp)
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: getI32Imm(AM.Disp));
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}
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/// getI8Imm - Return a target constant with the specified value, of type
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/// i8.
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inline SDOperand getI8Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i8);
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}
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/// getI16Imm - Return a target constant with the specified value, of type
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/// i16.
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inline SDOperand getI16Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i16);
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}
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/// getI32Imm - Return a target constant with the specified value, of type
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/// i32.
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inline SDOperand getI32Imm(unsigned Imm) {
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return CurDAG->getTargetConstant(Imm, MVT::i32);
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}
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/// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
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/// base register. Return the virtual register that holds this value.
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SDOperand getGlobalBaseReg();
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#ifndef NDEBUG
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unsigned Indent;
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#endif
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};
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}
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/// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
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/// when it has created a SelectionDAG for us to codegen.
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void X86DAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
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DEBUG(BB->dump());
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MachineFunction::iterator FirstMBB = BB;
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// Codegen the basic block.
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#ifndef NDEBUG
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DEBUG(std::cerr << "===== Instruction selection begins:\n");
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Indent = 0;
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#endif
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DAG.setRoot(SelectRoot(DAG.getRoot()));
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#ifndef NDEBUG
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DEBUG(std::cerr << "===== Instruction selection ends:\n");
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#endif
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CodeGenMap.clear();
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DAG.RemoveDeadNodes();
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// Emit machine code to BB.
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ScheduleAndEmitDAG(DAG);
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// If we are emitting FP stack code, scan the basic block to determine if this
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// block defines any FP values. If so, put an FP_REG_KILL instruction before
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// the terminator of the block.
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if (!Subtarget->hasSSE2()) {
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// Note that FP stack instructions *are* used in SSE code when returning
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// values, but these are not live out of the basic block, so we don't need
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// an FP_REG_KILL in this case either.
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bool ContainsFPCode = false;
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// Scan all of the machine instructions in these MBBs, checking for FP
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// stores.
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MachineFunction::iterator MBBI = FirstMBB;
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do {
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for (MachineBasicBlock::iterator I = MBBI->begin(), E = MBBI->end();
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!ContainsFPCode && I != E; ++I) {
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for (unsigned op = 0, e = I->getNumOperands(); op != e; ++op) {
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if (I->getOperand(op).isRegister() && I->getOperand(op).isDef() &&
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MRegisterInfo::isVirtualRegister(I->getOperand(op).getReg()) &&
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RegMap->getRegClass(I->getOperand(0).getReg()) ==
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X86::RFPRegisterClass) {
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ContainsFPCode = true;
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break;
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}
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}
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}
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} while (!ContainsFPCode && &*(MBBI++) != BB);
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// Check PHI nodes in successor blocks. These PHI's will be lowered to have
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// a copy of the input value in this block.
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if (!ContainsFPCode) {
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// Final check, check LLVM BB's that are successors to the LLVM BB
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// corresponding to BB for FP PHI nodes.
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const BasicBlock *LLVMBB = BB->getBasicBlock();
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const PHINode *PN;
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for (succ_const_iterator SI = succ_begin(LLVMBB), E = succ_end(LLVMBB);
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!ContainsFPCode && SI != E; ++SI) {
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for (BasicBlock::const_iterator II = SI->begin();
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(PN = dyn_cast<PHINode>(II)); ++II) {
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if (PN->getType()->isFloatingPoint()) {
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ContainsFPCode = true;
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break;
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}
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}
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}
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}
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// Finally, if we found any FP code, emit the FP_REG_KILL instruction.
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if (ContainsFPCode) {
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BuildMI(*BB, BB->getFirstTerminator(), X86::FP_REG_KILL, 0);
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++NumFPKill;
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}
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}
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}
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/// EmitSpecialCodeForMain - Emit any code that needs to be executed only in
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/// the main function.
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static void EmitSpecialCodeForMain(MachineBasicBlock *BB,
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MachineFrameInfo *MFI) {
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// Switch the FPU to 64-bit precision mode for better compatibility and speed.
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int CWFrameIdx = MFI->CreateStackObject(2, 2);
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addFrameReference(BuildMI(BB, X86::FNSTCW16m, 4), CWFrameIdx);
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// Set the high part to be 64-bit precision.
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addFrameReference(BuildMI(BB, X86::MOV8mi, 5),
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CWFrameIdx, 1).addImm(2);
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// Reload the modified control word now.
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addFrameReference(BuildMI(BB, X86::FLDCW16m, 4), CWFrameIdx);
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}
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void X86DAGToDAGISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
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// If this is main, emit special code for main.
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MachineBasicBlock *BB = MF.begin();
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if (Fn.hasExternalLinkage() && Fn.getName() == "main")
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EmitSpecialCodeForMain(BB, MF.getFrameInfo());
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}
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/// MatchAddress - Add the specified node to the specified addressing mode,
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/// returning true if it cannot be done. This just pattern matches for the
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/// addressing mode
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bool X86DAGToDAGISel::MatchAddress(SDOperand N, X86ISelAddressMode &AM,
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bool isRoot) {
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bool Available = false;
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// If N has already been selected, reuse the result unless in some very
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// specific cases.
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std::map<SDOperand, SDOperand>::iterator CGMI= CodeGenMap.find(N.getValue(0));
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if (CGMI != CodeGenMap.end()) {
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Available = true;
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}
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switch (N.getOpcode()) {
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default: break;
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case ISD::Constant:
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AM.Disp += cast<ConstantSDNode>(N)->getValue();
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return false;
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case X86ISD::Wrapper:
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// If both base and index components have been picked, we can't fit
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// the result available in the register in the addressing mode. Duplicate
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// GlobalAddress or ConstantPool as displacement.
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if (!Available || (AM.Base.Reg.Val && AM.IndexReg.Val)) {
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if (ConstantPoolSDNode *CP =
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dyn_cast<ConstantPoolSDNode>(N.getOperand(0))) {
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if (AM.CP == 0) {
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AM.CP = CP->get();
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AM.Align = CP->getAlignment();
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AM.Disp += CP->getOffset();
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return false;
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}
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} else if (GlobalAddressSDNode *G =
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dyn_cast<GlobalAddressSDNode>(N.getOperand(0))) {
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if (AM.GV == 0) {
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AM.GV = G->getGlobal();
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AM.Disp += G->getOffset();
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return false;
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}
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}
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}
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break;
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case ISD::FrameIndex:
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if (AM.BaseType == X86ISelAddressMode::RegBase && AM.Base.Reg.Val == 0) {
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AM.BaseType = X86ISelAddressMode::FrameIndexBase;
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AM.Base.FrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
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return false;
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}
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break;
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case ISD::SHL:
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if (!Available && AM.IndexReg.Val == 0 && AM.Scale == 1)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1))) {
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unsigned Val = CN->getValue();
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if (Val == 1 || Val == 2 || Val == 3) {
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AM.Scale = 1 << Val;
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SDOperand ShVal = N.Val->getOperand(0);
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (ShVal.Val->getOpcode() == ISD::ADD && ShVal.hasOneUse() &&
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isa<ConstantSDNode>(ShVal.Val->getOperand(1))) {
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AM.IndexReg = ShVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(ShVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() << Val;
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} else {
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AM.IndexReg = ShVal;
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}
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return false;
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}
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}
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break;
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case ISD::MUL:
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// X*[3,5,9] -> X+X*[2,4,8]
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if (!Available &&
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AM.BaseType == X86ISelAddressMode::RegBase &&
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AM.Base.Reg.Val == 0 &&
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AM.IndexReg.Val == 0)
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if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.Val->getOperand(1)))
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if (CN->getValue() == 3 || CN->getValue() == 5 || CN->getValue() == 9) {
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AM.Scale = unsigned(CN->getValue())-1;
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SDOperand MulVal = N.Val->getOperand(0);
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SDOperand Reg;
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// Okay, we know that we have a scale by now. However, if the scaled
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// value is an add of something and a constant, we can fold the
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// constant into the disp field here.
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if (MulVal.Val->getOpcode() == ISD::ADD && MulVal.hasOneUse() &&
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isa<ConstantSDNode>(MulVal.Val->getOperand(1))) {
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Reg = MulVal.Val->getOperand(0);
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ConstantSDNode *AddVal =
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cast<ConstantSDNode>(MulVal.Val->getOperand(1));
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AM.Disp += AddVal->getValue() * CN->getValue();
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} else {
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Reg = N.Val->getOperand(0);
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}
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AM.IndexReg = AM.Base.Reg = Reg;
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return false;
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}
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break;
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case ISD::ADD: {
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if (!Available) {
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X86ISelAddressMode Backup = AM;
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if (!MatchAddress(N.Val->getOperand(0), AM, false) &&
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!MatchAddress(N.Val->getOperand(1), AM, false))
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return false;
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AM = Backup;
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if (!MatchAddress(N.Val->getOperand(1), AM, false) &&
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!MatchAddress(N.Val->getOperand(0), AM, false))
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return false;
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AM = Backup;
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}
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break;
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}
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}
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// Is the base register already occupied?
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if (AM.BaseType != X86ISelAddressMode::RegBase || AM.Base.Reg.Val) {
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// If so, check to see if the scale index register is set.
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if (AM.IndexReg.Val == 0) {
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AM.IndexReg = N;
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AM.Scale = 1;
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return false;
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}
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// Otherwise, we cannot select it.
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return true;
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}
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// Default, generate it as a register.
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AM.BaseType = X86ISelAddressMode::RegBase;
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AM.Base.Reg = N;
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return false;
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}
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/// SelectAddr - returns true if it is able pattern match an addressing mode.
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/// It returns the operands which make up the maximal addressing mode it can
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/// match by reference.
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bool X86DAGToDAGISel::SelectAddr(SDOperand N, SDOperand &Base, SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (MatchAddress(N, AM))
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return false;
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if (AM.BaseType == X86ISelAddressMode::RegBase) {
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if (!AM.Base.Reg.Val)
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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}
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if (!AM.IndexReg.Val)
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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getAddressOperands(AM, Base, Scale, Index, Disp);
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return true;
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}
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/// SelectLEAAddr - it calls SelectAddr and determines if the maximal addressing
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/// mode it matches can be cost effectively emitted as an LEA instruction.
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/// For X86, it always is unless it's just a (Reg + const).
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bool X86DAGToDAGISel::SelectLEAAddr(SDOperand N, SDOperand &Base,
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SDOperand &Scale,
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SDOperand &Index, SDOperand &Disp) {
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X86ISelAddressMode AM;
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if (MatchAddress(N, AM))
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return false;
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unsigned Complexity = 0;
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if (AM.BaseType == X86ISelAddressMode::RegBase)
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if (AM.Base.Reg.Val)
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Complexity = 1;
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else
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AM.Base.Reg = CurDAG->getRegister(0, MVT::i32);
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else if (AM.BaseType == X86ISelAddressMode::FrameIndexBase)
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Complexity = 4;
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if (AM.IndexReg.Val)
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Complexity++;
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else
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AM.IndexReg = CurDAG->getRegister(0, MVT::i32);
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if (AM.Scale > 2)
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Complexity += 2;
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// Don't match just leal(,%reg,2). It's cheaper to do addl %reg, %reg
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else if (AM.Scale > 1)
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Complexity++;
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// FIXME: We are artificially lowering the criteria to turn ADD %reg, $GA
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// to a LEA. This is determined with some expermentation but is by no means
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// optimal (especially for code size consideration). LEA is nice because of
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// its three-address nature. Tweak the cost function again when we can run
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// convertToThreeAddress() at register allocation time.
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if (AM.GV || AM.CP)
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Complexity += 2;
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if (AM.Disp && (AM.Base.Reg.Val || AM.IndexReg.Val))
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Complexity++;
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if (Complexity > 2) {
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getAddressOperands(AM, Base, Scale, Index, Disp);
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return true;
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}
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|
return false;
|
|
}
|
|
|
|
bool X86DAGToDAGISel::TryFoldLoad(SDOperand P, SDOperand N,
|
|
SDOperand &Base, SDOperand &Scale,
|
|
SDOperand &Index, SDOperand &Disp) {
|
|
if (N.getOpcode() == ISD::LOAD &&
|
|
N.hasOneUse() &&
|
|
!CodeGenMap.count(N.getValue(0)) &&
|
|
(P.getNumOperands() == 1 || !isNonImmUse(P.Val, N.Val)))
|
|
return SelectAddr(N.getOperand(1), Base, Scale, Index, Disp);
|
|
return false;
|
|
}
|
|
|
|
static bool isRegister0(SDOperand Op) {
|
|
if (RegisterSDNode *R = dyn_cast<RegisterSDNode>(Op))
|
|
return (R->getReg() == 0);
|
|
return false;
|
|
}
|
|
|
|
/// getGlobalBaseReg - Output the instructions required to put the
|
|
/// base address to use for accessing globals into a register.
|
|
///
|
|
SDOperand X86DAGToDAGISel::getGlobalBaseReg() {
|
|
if (!GlobalBaseReg) {
|
|
// Insert the set of GlobalBaseReg into the first MBB of the function
|
|
MachineBasicBlock &FirstMBB = BB->getParent()->front();
|
|
MachineBasicBlock::iterator MBBI = FirstMBB.begin();
|
|
SSARegMap *RegMap = BB->getParent()->getSSARegMap();
|
|
// FIXME: when we get to LP64, we will need to create the appropriate
|
|
// type of register here.
|
|
GlobalBaseReg = RegMap->createVirtualRegister(X86::R32RegisterClass);
|
|
BuildMI(FirstMBB, MBBI, X86::MovePCtoStack, 0);
|
|
BuildMI(FirstMBB, MBBI, X86::POP32r, 1, GlobalBaseReg);
|
|
}
|
|
return CurDAG->getRegister(GlobalBaseReg, MVT::i32);
|
|
}
|
|
|
|
void X86DAGToDAGISel::Select(SDOperand &Result, SDOperand N) {
|
|
SDNode *Node = N.Val;
|
|
MVT::ValueType NVT = Node->getValueType(0);
|
|
unsigned Opc, MOpc;
|
|
unsigned Opcode = Node->getOpcode();
|
|
|
|
#ifndef NDEBUG
|
|
DEBUG(std::cerr << std::string(Indent, ' '));
|
|
DEBUG(std::cerr << "Selecting: ");
|
|
DEBUG(Node->dump(CurDAG));
|
|
DEBUG(std::cerr << "\n");
|
|
Indent += 2;
|
|
#endif
|
|
|
|
if (Opcode >= ISD::BUILTIN_OP_END && Opcode < X86ISD::FIRST_NUMBER) {
|
|
Result = N;
|
|
#ifndef NDEBUG
|
|
DEBUG(std::cerr << std::string(Indent-2, ' '));
|
|
DEBUG(std::cerr << "== ");
|
|
DEBUG(Node->dump(CurDAG));
|
|
DEBUG(std::cerr << "\n");
|
|
Indent -= 2;
|
|
#endif
|
|
return; // Already selected.
|
|
}
|
|
|
|
std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(N);
|
|
if (CGMI != CodeGenMap.end()) {
|
|
Result = CGMI->second;
|
|
#ifndef NDEBUG
|
|
DEBUG(std::cerr << std::string(Indent-2, ' '));
|
|
DEBUG(std::cerr << "== ");
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
DEBUG(std::cerr << "\n");
|
|
Indent -= 2;
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
switch (Opcode) {
|
|
default: break;
|
|
case X86ISD::GlobalBaseReg:
|
|
Result = getGlobalBaseReg();
|
|
return;
|
|
|
|
case ISD::ADD: {
|
|
// Turn ADD X, c to MOV32ri X+c. This cannot be done with tblgen'd
|
|
// code and is matched first so to prevent it from being turned into
|
|
// LEA32r X+c.
|
|
SDOperand N0 = N.getOperand(0);
|
|
SDOperand N1 = N.getOperand(1);
|
|
if (N.Val->getValueType(0) == MVT::i32 &&
|
|
N0.getOpcode() == X86ISD::Wrapper &&
|
|
N1.getOpcode() == ISD::Constant) {
|
|
unsigned Offset = (unsigned)cast<ConstantSDNode>(N1)->getValue();
|
|
SDOperand C(0, 0);
|
|
// TODO: handle ExternalSymbolSDNode.
|
|
if (GlobalAddressSDNode *G =
|
|
dyn_cast<GlobalAddressSDNode>(N0.getOperand(0))) {
|
|
C = CurDAG->getTargetGlobalAddress(G->getGlobal(), MVT::i32,
|
|
G->getOffset() + Offset);
|
|
} else if (ConstantPoolSDNode *CP =
|
|
dyn_cast<ConstantPoolSDNode>(N0.getOperand(0))) {
|
|
C = CurDAG->getTargetConstantPool(CP->get(), MVT::i32,
|
|
CP->getAlignment(),
|
|
CP->getOffset()+Offset);
|
|
}
|
|
|
|
if (C.Val) {
|
|
if (N.Val->hasOneUse()) {
|
|
Result = CurDAG->SelectNodeTo(N.Val, X86::MOV32ri, MVT::i32, C);
|
|
} else {
|
|
SDNode *ResNode = CurDAG->getTargetNode(X86::MOV32ri, MVT::i32, C);
|
|
Result = CodeGenMap[N] = SDOperand(ResNode, 0);
|
|
}
|
|
return;
|
|
}
|
|
}
|
|
|
|
// Other cases are handled by auto-generated code.
|
|
break;
|
|
}
|
|
|
|
case ISD::MULHU:
|
|
case ISD::MULHS: {
|
|
if (Opcode == ISD::MULHU)
|
|
switch (NVT) {
|
|
default: assert(0 && "Unsupported VT!");
|
|
case MVT::i8: Opc = X86::MUL8r; MOpc = X86::MUL8m; break;
|
|
case MVT::i16: Opc = X86::MUL16r; MOpc = X86::MUL16m; break;
|
|
case MVT::i32: Opc = X86::MUL32r; MOpc = X86::MUL32m; break;
|
|
}
|
|
else
|
|
switch (NVT) {
|
|
default: assert(0 && "Unsupported VT!");
|
|
case MVT::i8: Opc = X86::IMUL8r; MOpc = X86::IMUL8m; break;
|
|
case MVT::i16: Opc = X86::IMUL16r; MOpc = X86::IMUL16m; break;
|
|
case MVT::i32: Opc = X86::IMUL32r; MOpc = X86::IMUL32m; break;
|
|
}
|
|
|
|
unsigned LoReg, HiReg;
|
|
switch (NVT) {
|
|
default: assert(0 && "Unsupported VT!");
|
|
case MVT::i8: LoReg = X86::AL; HiReg = X86::AH; break;
|
|
case MVT::i16: LoReg = X86::AX; HiReg = X86::DX; break;
|
|
case MVT::i32: LoReg = X86::EAX; HiReg = X86::EDX; break;
|
|
}
|
|
|
|
SDOperand N0 = Node->getOperand(0);
|
|
SDOperand N1 = Node->getOperand(1);
|
|
|
|
bool foldedLoad = false;
|
|
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
|
|
foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
|
|
// MULHU and MULHS are commmutative
|
|
if (!foldedLoad) {
|
|
foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
|
|
if (foldedLoad) {
|
|
N0 = Node->getOperand(1);
|
|
N1 = Node->getOperand(0);
|
|
}
|
|
}
|
|
|
|
SDOperand Chain;
|
|
if (foldedLoad)
|
|
Select(Chain, N1.getOperand(0));
|
|
else
|
|
Chain = CurDAG->getEntryNode();
|
|
|
|
SDOperand InFlag(0, 0);
|
|
Select(N0, N0);
|
|
Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
|
|
N0, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
if (foldedLoad) {
|
|
Select(Tmp0, Tmp0);
|
|
Select(Tmp1, Tmp1);
|
|
Select(Tmp2, Tmp2);
|
|
Select(Tmp3, Tmp3);
|
|
SDNode *CNode =
|
|
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
|
|
Tmp2, Tmp3, Chain, InFlag);
|
|
Chain = SDOperand(CNode, 0);
|
|
InFlag = SDOperand(CNode, 1);
|
|
} else {
|
|
Select(N1, N1);
|
|
InFlag =
|
|
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
|
|
}
|
|
|
|
Result = CurDAG->getCopyFromReg(Chain, HiReg, NVT, InFlag);
|
|
CodeGenMap[N.getValue(0)] = Result;
|
|
if (foldedLoad) {
|
|
CodeGenMap[N1.getValue(1)] = Result.getValue(1);
|
|
AddHandleReplacement(N1.Val, 1, Result.Val, 1);
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
DEBUG(std::cerr << std::string(Indent-2, ' '));
|
|
DEBUG(std::cerr << "== ");
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
DEBUG(std::cerr << "\n");
|
|
Indent -= 2;
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
case ISD::SDIV:
|
|
case ISD::UDIV:
|
|
case ISD::SREM:
|
|
case ISD::UREM: {
|
|
bool isSigned = Opcode == ISD::SDIV || Opcode == ISD::SREM;
|
|
bool isDiv = Opcode == ISD::SDIV || Opcode == ISD::UDIV;
|
|
if (!isSigned)
|
|
switch (NVT) {
|
|
default: assert(0 && "Unsupported VT!");
|
|
case MVT::i8: Opc = X86::DIV8r; MOpc = X86::DIV8m; break;
|
|
case MVT::i16: Opc = X86::DIV16r; MOpc = X86::DIV16m; break;
|
|
case MVT::i32: Opc = X86::DIV32r; MOpc = X86::DIV32m; break;
|
|
}
|
|
else
|
|
switch (NVT) {
|
|
default: assert(0 && "Unsupported VT!");
|
|
case MVT::i8: Opc = X86::IDIV8r; MOpc = X86::IDIV8m; break;
|
|
case MVT::i16: Opc = X86::IDIV16r; MOpc = X86::IDIV16m; break;
|
|
case MVT::i32: Opc = X86::IDIV32r; MOpc = X86::IDIV32m; break;
|
|
}
|
|
|
|
unsigned LoReg, HiReg;
|
|
unsigned ClrOpcode, SExtOpcode;
|
|
switch (NVT) {
|
|
default: assert(0 && "Unsupported VT!");
|
|
case MVT::i8:
|
|
LoReg = X86::AL; HiReg = X86::AH;
|
|
ClrOpcode = X86::MOV8ri;
|
|
SExtOpcode = X86::CBW;
|
|
break;
|
|
case MVT::i16:
|
|
LoReg = X86::AX; HiReg = X86::DX;
|
|
ClrOpcode = X86::MOV16ri;
|
|
SExtOpcode = X86::CWD;
|
|
break;
|
|
case MVT::i32:
|
|
LoReg = X86::EAX; HiReg = X86::EDX;
|
|
ClrOpcode = X86::MOV32ri;
|
|
SExtOpcode = X86::CDQ;
|
|
break;
|
|
}
|
|
|
|
SDOperand N0 = Node->getOperand(0);
|
|
SDOperand N1 = Node->getOperand(1);
|
|
|
|
bool foldedLoad = false;
|
|
SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
|
|
foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
|
|
SDOperand Chain;
|
|
if (foldedLoad)
|
|
Select(Chain, N1.getOperand(0));
|
|
else
|
|
Chain = CurDAG->getEntryNode();
|
|
|
|
SDOperand InFlag(0, 0);
|
|
Select(N0, N0);
|
|
Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(LoReg, NVT),
|
|
N0, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
|
|
if (isSigned) {
|
|
// Sign extend the low part into the high part.
|
|
InFlag =
|
|
SDOperand(CurDAG->getTargetNode(SExtOpcode, MVT::Flag, InFlag), 0);
|
|
} else {
|
|
// Zero out the high part, effectively zero extending the input.
|
|
SDOperand ClrNode =
|
|
SDOperand(CurDAG->getTargetNode(ClrOpcode, NVT,
|
|
CurDAG->getTargetConstant(0, NVT)), 0);
|
|
Chain = CurDAG->getCopyToReg(Chain, CurDAG->getRegister(HiReg, NVT),
|
|
ClrNode, InFlag);
|
|
InFlag = Chain.getValue(1);
|
|
}
|
|
|
|
if (foldedLoad) {
|
|
Select(Tmp0, Tmp0);
|
|
Select(Tmp1, Tmp1);
|
|
Select(Tmp2, Tmp2);
|
|
Select(Tmp3, Tmp3);
|
|
SDNode *CNode =
|
|
CurDAG->getTargetNode(MOpc, MVT::Other, MVT::Flag, Tmp0, Tmp1,
|
|
Tmp2, Tmp3, Chain, InFlag);
|
|
Chain = SDOperand(CNode, 0);
|
|
InFlag = SDOperand(CNode, 1);
|
|
} else {
|
|
Select(N1, N1);
|
|
InFlag =
|
|
SDOperand(CurDAG->getTargetNode(Opc, MVT::Flag, N1, InFlag), 0);
|
|
}
|
|
|
|
Result = CurDAG->getCopyFromReg(Chain, isDiv ? LoReg : HiReg,
|
|
NVT, InFlag);
|
|
CodeGenMap[N.getValue(0)] = Result;
|
|
if (foldedLoad) {
|
|
CodeGenMap[N1.getValue(1)] = Result.getValue(1);
|
|
AddHandleReplacement(N1.Val, 1, Result.Val, 1);
|
|
}
|
|
|
|
#ifndef NDEBUG
|
|
DEBUG(std::cerr << std::string(Indent-2, ' '));
|
|
DEBUG(std::cerr << "== ");
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
DEBUG(std::cerr << "\n");
|
|
Indent -= 2;
|
|
#endif
|
|
return;
|
|
}
|
|
|
|
case ISD::TRUNCATE: {
|
|
unsigned Reg;
|
|
MVT::ValueType VT;
|
|
switch (Node->getOperand(0).getValueType()) {
|
|
default: assert(0 && "Unknown truncate!");
|
|
case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
|
|
case MVT::i32: Reg = X86::EAX; Opc = X86::MOV32rr; VT = MVT::i32; break;
|
|
}
|
|
SDOperand Tmp0, Tmp1;
|
|
Select(Tmp0, Node->getOperand(0));
|
|
Select(Tmp1, SDOperand(CurDAG->getTargetNode(Opc, VT, Tmp0), 0));
|
|
SDOperand InFlag = SDOperand(0,0);
|
|
Result = CurDAG->getCopyToReg(CurDAG->getEntryNode(), Reg, Tmp1, InFlag);
|
|
SDOperand Chain = Result.getValue(0);
|
|
InFlag = Result.getValue(1);
|
|
|
|
switch (NVT) {
|
|
default: assert(0 && "Unknown truncate!");
|
|
case MVT::i8: Reg = X86::AL; Opc = X86::MOV8rr; VT = MVT::i8; break;
|
|
case MVT::i16: Reg = X86::AX; Opc = X86::MOV16rr; VT = MVT::i16; break;
|
|
}
|
|
|
|
Result = CurDAG->getCopyFromReg(Chain, Reg, VT, InFlag);
|
|
if (N.Val->hasOneUse())
|
|
Result = CurDAG->SelectNodeTo(N.Val, Opc, VT, Result);
|
|
else
|
|
Result = CodeGenMap[N] =
|
|
SDOperand(CurDAG->getTargetNode(Opc, VT, Result), 0);
|
|
|
|
#ifndef NDEBUG
|
|
DEBUG(std::cerr << std::string(Indent-2, ' '));
|
|
DEBUG(std::cerr << "== ");
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
DEBUG(std::cerr << "\n");
|
|
Indent -= 2;
|
|
#endif
|
|
return;
|
|
}
|
|
}
|
|
|
|
SelectCode(Result, N);
|
|
#ifndef NDEBUG
|
|
DEBUG(std::cerr << std::string(Indent-2, ' '));
|
|
DEBUG(std::cerr << "=> ");
|
|
DEBUG(Result.Val->dump(CurDAG));
|
|
DEBUG(std::cerr << "\n");
|
|
Indent -= 2;
|
|
#endif
|
|
}
|
|
|
|
/// createX86ISelDag - This pass converts a legalized DAG into a
|
|
/// X86-specific DAG, ready for instruction scheduling.
|
|
///
|
|
FunctionPass *llvm::createX86ISelDag(X86TargetMachine &TM) {
|
|
return new X86DAGToDAGISel(TM);
|
|
}
|