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8ab5fe574a
handling. This makes the lower argument code significantly simpler (we only need to handle legal argument types). Incidentally, this also implements support for vector argument registers, so long as they are not on the stack. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28331 91177308-0d34-0410-b5e6-96231b3b80d8
194 lines
8.0 KiB
C++
194 lines
8.0 KiB
C++
//===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Chris Lattner and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that PPC uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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#define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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#include "llvm/Target/TargetLowering.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "PPC.h"
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namespace llvm {
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namespace PPCISD {
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enum NodeType {
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// Start the numbering where the builting ops and target ops leave off.
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FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
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/// FSEL - Traditional three-operand fsel node.
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///
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FSEL,
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/// FCFID - The FCFID instruction, taking an f64 operand and producing
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/// and f64 value containing the FP representation of the integer that
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/// was temporarily in the f64 operand.
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FCFID,
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/// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
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/// operand, producing an f64 value containing the integer representation
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/// of that FP value.
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FCTIDZ, FCTIWZ,
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/// STFIWX - The STFIWX instruction. The first operand is an input token
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/// chain, then an f64 value to store, then an address to store it to,
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/// then a SRCVALUE for the address.
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STFIWX,
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// VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
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// three v4f32 operands and producing a v4f32 result.
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VMADDFP, VNMSUBFP,
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/// VPERM - The PPC VPERM Instruction.
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///
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VPERM,
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/// Hi/Lo - These represent the high and low 16-bit parts of a global
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/// address respectively. These nodes have two operands, the first of
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/// which must be a TargetGlobalAddress, and the second of which must be a
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/// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
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/// though these are usually folded into other nodes.
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Hi, Lo,
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/// GlobalBaseReg - On Darwin, this node represents the result of the mflr
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/// at function entry, used for PIC code.
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GlobalBaseReg,
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/// These nodes represent the 32-bit PPC shifts that operate on 6-bit
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/// shift amounts. These nodes are generated by the multi-precision shift
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/// code.
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SRL, SRA, SHL,
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/// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
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/// registers.
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EXTSW_32,
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/// STD_32 - This is the STD instruction for use with "32-bit" registers.
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STD_32,
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/// CALL - A function call.
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CALL,
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/// Return with a flag operand, matched by 'blr'
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RET_FLAG,
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/// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
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/// This copies the bits corresponding to the specified CRREG into the
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/// resultant GPR. Bits corresponding to other CR regs are undefined.
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MFCR,
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/// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
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/// instructions. For lack of better number, we use the opcode number
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/// encoding for the OPC field to identify the compare. For example, 838
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/// is VCMPGTSH.
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VCMP,
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/// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
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/// altivec VCMP*o instructions. For lack of better number, we use the
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/// opcode number encoding for the OPC field to identify the compare. For
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/// example, 838 is VCMPGTSH.
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VCMPo,
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/// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
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/// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
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/// condition register to branch on, OPC is the branch opcode to use (e.g.
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/// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
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/// an optional input flag argument.
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COND_BRANCH
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};
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}
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/// Define some predicates that are used for node matching.
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namespace PPC {
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/// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUHUM instruction.
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bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary);
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/// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
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/// VPKUWUM instruction.
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bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary);
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/// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
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/// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
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/// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
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bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
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/// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
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/// amount, otherwise return -1.
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int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
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/// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
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/// specifies a splat of a single element that is suitable for input to
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/// VSPLTB/VSPLTH/VSPLTW.
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bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
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/// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
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/// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
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unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
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/// get_VSPLTI_elt - If this is a build_vector of constants which can be
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/// formed by using a vspltis[bhw] instruction of the specified element
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/// size, return the constant being splatted. The ByteSize field indicates
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/// the number of bytes of each element [124] -> [bhw].
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SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
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}
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class PPCTargetLowering : public TargetLowering {
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int VarArgsFrameIndex; // FrameIndex for start of varargs area.
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int ReturnAddrIndex; // FrameIndex for return slot.
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public:
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PPCTargetLowering(TargetMachine &TM);
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/// getTargetNodeName() - This method returns the name of a target specific
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/// DAG node.
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virtual const char *getTargetNodeName(unsigned Opcode) const;
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
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virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
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virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
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uint64_t Mask,
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uint64_t &KnownZero,
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uint64_t &KnownOne,
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unsigned Depth = 0) const;
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/// LowerCallTo - This hook lowers an abstract call to a function into an
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/// actual call.
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virtual std::pair<SDOperand, SDOperand>
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LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
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unsigned CC,
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bool isTailCall, SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG);
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virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
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MachineBasicBlock *MBB);
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ConstraintType getConstraintType(char ConstraintLetter) const;
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std::vector<unsigned>
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getRegClassForInlineAsmConstraint(const std::string &Constraint,
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MVT::ValueType VT) const;
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bool isOperandValidForConstraint(SDOperand Op, char ConstraintLetter);
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/// isLegalAddressImmediate - Return true if the integer value can be used
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/// as the offset of the target addressing mode.
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virtual bool isLegalAddressImmediate(int64_t V) const;
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};
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}
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#endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
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