mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-11 09:29:20 +00:00
b4dc0233c9
This was done with the following sed invocation to catch label lines demarking function boundaries:
sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8
248 lines
6.4 KiB
LLVM
248 lines
6.4 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
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; AVX2 Logical Shift Left
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define <16 x i16> @test_sllw_1(<16 x i16> %InVec) {
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entry:
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%shl = shl <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_1:
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; CHECK: vpsllw $0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sllw_2(<16 x i16> %InVec) {
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entry:
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%shl = shl <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_2:
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; CHECK: vpaddw %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sllw_3(<16 x i16> %InVec) {
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entry:
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%shl = shl <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sllw_3:
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; CHECK: vxorps %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_slld_1(<8 x i32> %InVec) {
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entry:
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%shl = shl <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_slld_1:
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; CHECK: vpslld $0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_slld_2(<8 x i32> %InVec) {
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entry:
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%shl = shl <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_slld_2:
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; CHECK: vpaddd %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_slld_3(<8 x i32> %InVec) {
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entry:
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%shl = shl <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_slld_3:
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; CHECK: vxorps %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_sllq_1(<4 x i64> %InVec) {
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entry:
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%shl = shl <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_1:
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; CHECK: vpsllq $0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_sllq_2(<4 x i64> %InVec) {
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entry:
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%shl = shl <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_2:
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; CHECK: vpaddq %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_sllq_3(<4 x i64> %InVec) {
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entry:
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%shl = shl <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_sllq_3:
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; CHECK: vxorps %ymm0, %ymm0, %ymm0
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; CHECK: ret
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; AVX2 Arithmetic Shift
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define <16 x i16> @test_sraw_1(<16 x i16> %InVec) {
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entry:
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%shl = ashr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_1:
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; CHECK: vpsraw $0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sraw_2(<16 x i16> %InVec) {
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entry:
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%shl = ashr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_2:
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; CHECK: vpsraw $1, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_sraw_3(<16 x i16> %InVec) {
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entry:
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%shl = ashr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_sraw_3:
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; CHECK: vpsraw $16, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srad_1(<8 x i32> %InVec) {
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entry:
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%shl = ashr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srad_1:
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; CHECK: vpsrad $0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srad_2(<8 x i32> %InVec) {
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entry:
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%shl = ashr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srad_2:
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; CHECK: vpsrad $1, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srad_3(<8 x i32> %InVec) {
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entry:
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%shl = ashr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srad_3:
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; CHECK: vpsrad $32, %ymm0, %ymm0
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; CHECK: ret
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; SSE Logical Shift Right
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define <16 x i16> @test_srlw_1(<16 x i16> %InVec) {
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entry:
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%shl = lshr <16 x i16> %InVec, <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_1:
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; CHECK: vpsrlw $0, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_srlw_2(<16 x i16> %InVec) {
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entry:
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%shl = lshr <16 x i16> %InVec, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_2:
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; CHECK: vpsrlw $1, %ymm0, %ymm0
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; CHECK: ret
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define <16 x i16> @test_srlw_3(<16 x i16> %InVec) {
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entry:
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%shl = lshr <16 x i16> %InVec, <i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16>
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ret <16 x i16> %shl
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}
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; CHECK-LABEL: test_srlw_3:
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; CHECK: vxorps %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srld_1(<8 x i32> %InVec) {
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entry:
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%shl = lshr <8 x i32> %InVec, <i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srld_1:
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; CHECK: vpsrld $0, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srld_2(<8 x i32> %InVec) {
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entry:
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%shl = lshr <8 x i32> %InVec, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srld_2:
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; CHECK: vpsrld $1, %ymm0, %ymm0
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; CHECK: ret
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define <8 x i32> @test_srld_3(<8 x i32> %InVec) {
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entry:
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%shl = lshr <8 x i32> %InVec, <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>
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ret <8 x i32> %shl
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}
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; CHECK-LABEL: test_srld_3:
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; CHECK: vxorps %ymm0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_srlq_1(<4 x i64> %InVec) {
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entry:
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%shl = lshr <4 x i64> %InVec, <i64 0, i64 0, i64 0, i64 0>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_1:
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; CHECK: vpsrlq $0, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_srlq_2(<4 x i64> %InVec) {
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entry:
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%shl = lshr <4 x i64> %InVec, <i64 1, i64 1, i64 1, i64 1>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_2:
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; CHECK: vpsrlq $1, %ymm0, %ymm0
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; CHECK: ret
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define <4 x i64> @test_srlq_3(<4 x i64> %InVec) {
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entry:
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%shl = lshr <4 x i64> %InVec, <i64 64, i64 64, i64 64, i64 64>
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ret <4 x i64> %shl
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}
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; CHECK-LABEL: test_srlq_3:
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; CHECK: vxorps %ymm0, %ymm0, %ymm0
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; CHECK: ret
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