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https://github.com/c64scene-ar/llvm-6502.git
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3bf51cf302
I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@197041 91177308-0d34-0410-b5e6-96231b3b80d8
156 lines
3.7 KiB
LLVM
156 lines
3.7 KiB
LLVM
; RUN: llc < %s -march=x86-64 -mtriple=x86_64-apple-darwin -mcpu=knl --show-mc-encoding| FileCheck %s
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; CHECK-LABEL: @test1
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; CHECK: vmovd %xmm0, %eax ## encoding: [0x62
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; CHECK: ret
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define i32 @test1(float %x) {
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%res = bitcast float %x to i32
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ret i32 %res
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}
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; CHECK-LABEL: @test2
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; CHECK: vmovd %edi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test2(i32 %x) {
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%res = insertelement <4 x i32>undef, i32 %x, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test3
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; CHECK: vmovq %rdi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <2 x i64> @test3(i64 %x) {
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%res = insertelement <2 x i64>undef, i64 %x, i32 0
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ret <2 x i64>%res
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}
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; CHECK-LABEL: @test4
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; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test4(i32* %x) {
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%y = load i32* %x
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%res = insertelement <4 x i32>undef, i32 %y, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test5
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; CHECK: vmovss %xmm0, (%rdi) ## encoding: [0x62
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; CHECK: ret
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define void @test5(float %x, float* %y) {
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store float %x, float* %y, align 4
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ret void
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}
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; CHECK-LABEL: @test6
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; CHECK: vmovsd %xmm0, (%rdi) ## encoding: [0x62
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; CHECK: ret
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define void @test6(double %x, double* %y) {
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store double %x, double* %y, align 8
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ret void
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}
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; CHECK-LABEL: @test7
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; CHECK: vmovss (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define float @test7(i32* %x) {
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%y = load i32* %x
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%res = bitcast i32 %y to float
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ret float %res
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}
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; CHECK-LABEL: @test8
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; CHECK: vmovd %xmm0, %eax ## encoding: [0x62
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; CHECK: ret
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define i32 @test8(<4 x i32> %x) {
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%res = extractelement <4 x i32> %x, i32 0
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ret i32 %res
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}
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; CHECK-LABEL: @test9
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; CHECK: vmovq %xmm0, %rax ## encoding: [0x62
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; CHECK: ret
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define i64 @test9(<2 x i64> %x) {
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%res = extractelement <2 x i64> %x, i32 0
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ret i64 %res
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}
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; CHECK-LABEL: @test10
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; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test10(i32* %x) {
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%y = load i32* %x, align 4
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%res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test11
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; CHECK: vmovss (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x float> @test11(float* %x) {
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%y = load float* %x, align 4
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%res = insertelement <4 x float>zeroinitializer, float %y, i32 0
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ret <4 x float>%res
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}
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; CHECK-LABEL: @test12
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; CHECK: vmovsd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <2 x double> @test12(double* %x) {
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%y = load double* %x, align 8
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%res = insertelement <2 x double>zeroinitializer, double %y, i32 0
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ret <2 x double>%res
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}
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; CHECK-LABEL: @test13
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; CHECK: vmovq %rdi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <2 x i64> @test13(i64 %x) {
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%res = insertelement <2 x i64>zeroinitializer, i64 %x, i32 0
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ret <2 x i64>%res
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}
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; CHECK-LABEL: @test14
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; CHECK: vmovd %edi, %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test14(i32 %x) {
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%res = insertelement <4 x i32>zeroinitializer, i32 %x, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: @test15
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; CHECK: vmovd (%rdi), %xmm0 ## encoding: [0x62
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; CHECK: ret
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define <4 x i32> @test15(i32* %x) {
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%y = load i32* %x, align 4
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%res = insertelement <4 x i32>zeroinitializer, i32 %y, i32 0
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ret <4 x i32>%res
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}
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; CHECK-LABEL: test16
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; CHECK: vmovdqu32
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; CHECK: ret
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define <16 x i32> @test16(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%res = load <16 x i32>* %vaddr, align 1
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test17
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; CHECK: vmovdqa32
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; CHECK: ret
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define <16 x i32> @test17(i8 * %addr) {
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%vaddr = bitcast i8* %addr to <16 x i32>*
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%res = load <16 x i32>* %vaddr, align 64
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ret <16 x i32>%res
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}
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; CHECK-LABEL: test18
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; CHECK: vmovdqa64
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; CHECK: ret
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define void @test18(i8 * %addr, <8 x i64> %data) {
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%vaddr = bitcast i8* %addr to <8 x i64>*
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store <8 x i64>%data, <8 x i64>* %vaddr, align 64
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ret void
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}
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