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5a70dd1d82
Similar to gep (r230786) and load (r230794) changes.
Similar migration script can be used to update test cases, which
successfully migrated all of LLVM and Polly, but about 4 test cases
needed manually changes in Clang.
(this script will read the contents of stdin and massage it into stdout
- wrap it in the 'apply.sh' script shown in previous commits + xargs to
apply it over a large set of test cases)
import fileinput
import sys
import re
rep = re.compile(r"(getelementptr(?:\s+inbounds)?\s*\()((<\d*\s+x\s+)?([^@]*?)(|\s*addrspace\(\d+\))\s*\*(?(3)>)\s*)(?=$|%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|zeroinitializer|<|\[\[[a-zA-Z]|\{\{)", re.MULTILINE | re.DOTALL)
def conv(match):
line = match.group(1)
line += match.group(4)
line += ", "
line += match.group(2)
return line
line = sys.stdin.read()
off = 0
for match in re.finditer(rep, line):
sys.stdout.write(line[off:match.start()])
sys.stdout.write(conv(match))
off = match.end()
sys.stdout.write(line[off:])
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232184 91177308-0d34-0410-b5e6-96231b3b80d8
27 lines
1.1 KiB
LLVM
27 lines
1.1 KiB
LLVM
; RUN: opt < %s -basicaa -gvn -tsan -S | FileCheck %s
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; TSAN conflicts with load widening. Make sure the load widening is off with -tsan.
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; 32-bit little endian target.
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
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%struct_of_8_bytes_4_aligned = type { i32, i8, i8, i8, i8}
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@f = global %struct_of_8_bytes_4_aligned zeroinitializer, align 4
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; Accessing bytes 4 and 6, not ok to widen to i32 if sanitize_thread is set.
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define i32 @test_widening_bad(i8* %P) nounwind ssp noredzone sanitize_thread {
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entry:
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%tmp = load i8, i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned, %struct_of_8_bytes_4_aligned* @f, i64 0, i32 1), align 4
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%conv = zext i8 %tmp to i32
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%tmp1 = load i8, i8* getelementptr inbounds (%struct_of_8_bytes_4_aligned, %struct_of_8_bytes_4_aligned* @f, i64 0, i32 3), align 1
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%conv2 = zext i8 %tmp1 to i32
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%add = add nsw i32 %conv, %conv2
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ret i32 %add
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; CHECK: @test_widening_bad
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; CHECK: call void @__tsan_read1
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; CHECK: call void @__tsan_read1
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; CHECK-NOT: call void @__tsan_read4
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; CHECK: ret i32
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}
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