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https://github.com/c64scene-ar/llvm-6502.git
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167974 91177308-0d34-0410-b5e6-96231b3b80d8
130 lines
3.2 KiB
C++
130 lines
3.2 KiB
C++
//===-- HexagonBaseInfo.h - Top level definitions for Hexagon --*- C++ -*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains small standalone helper functions and enum definitions for
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// the Hexagon target useful for the compiler back-end and the MC libraries.
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// As such, it deliberately does not include references to LLVM core
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// code gen types, passes, etc..
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//
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//===----------------------------------------------------------------------===//
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#ifndef HEXAGONBASEINFO_H
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#define HEXAGONBASEINFO_H
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namespace llvm {
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/// HexagonII - This namespace holds all of the target specific flags that
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/// instruction info tracks.
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///
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namespace HexagonII {
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// *** The code below must match HexagonInstrFormat*.td *** //
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// Insn types.
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// *** Must match HexagonInstrFormat*.td ***
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enum Type {
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TypePSEUDO = 0,
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TypeALU32 = 1,
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TypeCR = 2,
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TypeJR = 3,
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TypeJ = 4,
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TypeLD = 5,
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TypeST = 6,
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TypeSYSTEM = 7,
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TypeXTYPE = 8,
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TypeMEMOP = 9,
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TypeNV = 10,
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TypePREFIX = 30, // Such as extenders.
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TypeMARKER = 31 // Such as end of a HW loop.
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};
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enum SubTarget {
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HasV2SubT = 0xf,
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HasV2SubTOnly = 0x1,
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NoV2SubT = 0x0,
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HasV3SubT = 0xe,
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HasV3SubTOnly = 0x2,
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NoV3SubT = 0x1,
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HasV4SubT = 0xc,
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NoV4SubT = 0x3,
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HasV5SubT = 0x8,
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NoV5SubT = 0x7
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};
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enum AddrMode {
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NoAddrMode = 0, // No addressing mode
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Absolute = 1, // Absolute addressing mode
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AbsoluteSet = 2, // Absolute set addressing mode
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BaseImmOffset = 3, // Indirect with offset
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BaseLongOffset = 4, // Indirect with long offset
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BaseRegOffset = 5 // Indirect with register offset
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};
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// MCInstrDesc TSFlags
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// *** Must match HexagonInstrFormat*.td ***
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enum {
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// This 5-bit field describes the insn type.
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TypePos = 0,
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TypeMask = 0x1f,
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// Solo instructions.
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SoloPos = 5,
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SoloMask = 0x1,
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// Predicated instructions.
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PredicatedPos = 6,
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PredicatedMask = 0x1,
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PredicatedNewPos = 7,
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PredicatedNewMask = 0x1,
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// Stores that can be newified.
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mayNVStorePos = 8,
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mayNVStoreMask = 0x1,
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// Dot new value store instructions.
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NVStorePos = 9,
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NVStoreMask = 0x1,
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// Extendable insns.
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ExtendablePos = 10,
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ExtendableMask = 0x1,
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// Insns must be extended.
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ExtendedPos = 11,
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ExtendedMask = 0x1,
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// Which operand may be extended.
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ExtendableOpPos = 12,
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ExtendableOpMask = 0x7,
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// Signed or unsigned range.
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ExtentSignedPos = 15,
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ExtentSignedMask = 0x1,
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// Number of bits of range before extending operand.
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ExtentBitsPos = 16,
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ExtentBitsMask = 0x1f,
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// Valid subtargets
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validSubTargetPos = 21,
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validSubTargetMask = 0xf,
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// Addressing mode for load/store instructions
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AddrModePos = 25,
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AddrModeMask = 0xf
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};
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// *** The code above must match HexagonInstrFormat*.td *** //
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} // End namespace HexagonII.
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} // End namespace llvm.
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#endif
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