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https://github.com/c64scene-ar/llvm-6502.git
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8b19e56051
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55693 91177308-0d34-0410-b5e6-96231b3b80d8
191 lines
5.6 KiB
C++
191 lines
5.6 KiB
C++
//===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the X86-specific support for the FastISel class. Much
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// of the target-specific code is generated by tablegen in the file
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// X86GenFastISel.inc, which is #included here.
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrBuilder.h"
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#include "X86ISelLowering.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86TargetMachine.h"
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#include "llvm/CodeGen/FastISel.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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class X86FastISel : public FastISel {
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/// Subtarget - Keep a pointer to the X86Subtarget around so that we can
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/// make the right decision when generating code for different targets.
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const X86Subtarget *Subtarget;
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public:
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explicit X86FastISel(MachineFunction &mf) : FastISel(mf) {
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Subtarget = &TM.getSubtarget<X86Subtarget>();
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}
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virtual bool
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TargetSelectInstruction(Instruction *I,
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DenseMap<const Value *, unsigned> &ValueMap,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
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MachineBasicBlock *MBB);
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#include "X86GenFastISel.inc"
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private:
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bool X86SelectConstAddr(Value *V,
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DenseMap<const Value *, unsigned> &ValueMap,
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MachineBasicBlock *MBB, unsigned &Op0);
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bool X86SelectLoad(Instruction *I,
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DenseMap<const Value *, unsigned> &ValueMap,
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MachineBasicBlock *MBB);
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};
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/// X86SelectConstAddr - Select and emit code to materialize constant address.
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///
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bool X86FastISel::X86SelectConstAddr(Value *V,
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DenseMap<const Value *, unsigned> &ValueMap,
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MachineBasicBlock *MBB,
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unsigned &Op0) {
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// FIXME: Only GlobalAddress for now.
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GlobalValue *GV = dyn_cast<GlobalValue>(V);
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if (!GV)
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return false;
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if (Subtarget->GVRequiresExtraLoad(GV, TM, false)) {
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// Issue load from stub if necessary.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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if (TLI.getPointerTy() == MVT::i32) {
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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} else {
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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}
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Op0 = createResultReg(RC);
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X86AddressMode AM;
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AM.GV = GV;
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addFullAddress(BuildMI(MBB, TII.get(Opc), Op0), AM);
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}
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return true;
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}
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/// X86SelectLoad - Select and emit code to implement load instructions.
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///
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bool X86FastISel::X86SelectLoad(Instruction *I,
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DenseMap<const Value *, unsigned> &ValueMap,
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MachineBasicBlock *MBB) {
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MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
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if (VT == MVT::Other || !VT.isSimple())
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// Unhandled type. Halt "fast" selection and bail.
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return false;
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if (VT == MVT::iPTR)
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// Use pointer type.
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VT = TLI.getPointerTy();
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// We only handle legal types. For example, on x86-32 the instruction
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// selector contains all of the 64-bit instructions from x86-64,
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// under the assumption that i64 won't be used if the target doesn't
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// support it.
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if (!TLI.isTypeLegal(VT))
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return false;
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Value *V = I->getOperand(0);
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unsigned Op0 = getRegForValue(V, ValueMap);
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if (Op0 == 0) {
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// Handle constant load address.
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if (!isa<Constant>(V) || !X86SelectConstAddr(V, ValueMap, MBB, Op0))
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// Unhandled operand. Halt "fast" selection and bail.
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return false;
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}
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// Get opcode and regclass of the output for the given load instruction.
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unsigned Opc = 0;
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const TargetRegisterClass *RC = NULL;
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switch (VT.getSimpleVT()) {
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default: return false;
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case MVT::i8:
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Opc = X86::MOV8rm;
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RC = X86::GR8RegisterClass;
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break;
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case MVT::i16:
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Opc = X86::MOV16rm;
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RC = X86::GR16RegisterClass;
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break;
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case MVT::i32:
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Opc = X86::MOV32rm;
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RC = X86::GR32RegisterClass;
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break;
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case MVT::i64:
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// Must be in x86-64 mode.
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Opc = X86::MOV64rm;
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RC = X86::GR64RegisterClass;
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break;
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case MVT::f32:
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if (Subtarget->hasSSE1()) {
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Opc = X86::MOVSSrm;
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RC = X86::FR32RegisterClass;
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} else {
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Opc = X86::LD_Fp32m;
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RC = X86::RFP32RegisterClass;
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}
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break;
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case MVT::f64:
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if (Subtarget->hasSSE2()) {
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Opc = X86::MOVSDrm;
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RC = X86::FR64RegisterClass;
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} else {
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Opc = X86::LD_Fp64m;
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RC = X86::RFP64RegisterClass;
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}
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break;
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case MVT::f80:
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Opc = X86::LD_Fp80m;
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RC = X86::RFP80RegisterClass;
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break;
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}
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unsigned ResultReg = createResultReg(RC);
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X86AddressMode AM;
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if (Op0)
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// Address is in register.
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AM.Base.Reg = Op0;
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else
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AM.GV = cast<GlobalValue>(V);
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addFullAddress(BuildMI(MBB, TII.get(Opc), ResultReg), AM);
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UpdateValueMap(I, ResultReg, ValueMap);
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return true;
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}
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bool
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X86FastISel::TargetSelectInstruction(Instruction *I,
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DenseMap<const Value *, unsigned> &ValueMap,
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DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap,
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MachineBasicBlock *MBB) {
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switch (I->getOpcode()) {
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default: break;
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case Instruction::Load:
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return X86SelectLoad(I, ValueMap, MBB);
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}
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return false;
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}
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namespace llvm {
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llvm::FastISel *X86::createFastISel(MachineFunction &mf) {
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return new X86FastISel(mf);
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}
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}
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