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define below all header includes in the lib/CodeGen/... tree. While the current modules implementation doesn't check for this kind of ODR violation yet, it is likely to grow support for it in the future. It also removes one layer of macro pollution across all the included headers. Other sub-trees will follow. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@206837 91177308-0d34-0410-b5e6-96231b3b80d8
249 lines
8.4 KiB
C++
249 lines
8.4 KiB
C++
//===-- InterferenceCache.cpp - Caching per-block interference ---------*--===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// InterferenceCache remembers per-block interference in LiveIntervalUnions.
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//
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//===----------------------------------------------------------------------===//
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#include "InterferenceCache.h"
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#include "llvm/CodeGen/LiveIntervalAnalysis.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Target/TargetRegisterInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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// Static member used for null interference cursors.
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InterferenceCache::BlockInterference InterferenceCache::Cursor::NoInterference;
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// Initializes PhysRegEntries (instead of a SmallVector, PhysRegEntries is a
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// buffer of size NumPhysRegs to speed up alloc/clear for targets with large
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// reg files). Calloced memory is used for good form, and quites tools like
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// Valgrind too, but zero initialized memory is not required by the algorithm:
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// this is because PhysRegEntries works like a SparseSet and its entries are
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// only valid when there is a corresponding CacheEntries assignment. There is
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// also support for when pass managers are reused for targets with different
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// numbers of PhysRegs: in this case PhysRegEntries is freed and reinitialized.
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void InterferenceCache::reinitPhysRegEntries() {
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if (PhysRegEntriesCount == TRI->getNumRegs()) return;
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free(PhysRegEntries);
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PhysRegEntriesCount = TRI->getNumRegs();
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PhysRegEntries = (unsigned char*)
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calloc(PhysRegEntriesCount, sizeof(unsigned char));
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}
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void InterferenceCache::init(MachineFunction *mf,
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LiveIntervalUnion *liuarray,
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SlotIndexes *indexes,
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LiveIntervals *lis,
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const TargetRegisterInfo *tri) {
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MF = mf;
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LIUArray = liuarray;
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TRI = tri;
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reinitPhysRegEntries();
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for (unsigned i = 0; i != CacheEntries; ++i)
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Entries[i].clear(mf, indexes, lis);
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}
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InterferenceCache::Entry *InterferenceCache::get(unsigned PhysReg) {
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unsigned E = PhysRegEntries[PhysReg];
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if (E < CacheEntries && Entries[E].getPhysReg() == PhysReg) {
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if (!Entries[E].valid(LIUArray, TRI))
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Entries[E].revalidate(LIUArray, TRI);
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return &Entries[E];
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}
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// No valid entry exists, pick the next round-robin entry.
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E = RoundRobin;
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if (++RoundRobin == CacheEntries)
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RoundRobin = 0;
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for (unsigned i = 0; i != CacheEntries; ++i) {
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// Skip entries that are in use.
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if (Entries[E].hasRefs()) {
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if (++E == CacheEntries)
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E = 0;
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continue;
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}
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Entries[E].reset(PhysReg, LIUArray, TRI, MF);
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PhysRegEntries[PhysReg] = E;
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return &Entries[E];
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}
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llvm_unreachable("Ran out of interference cache entries.");
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}
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/// revalidate - LIU contents have changed, update tags.
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void InterferenceCache::Entry::revalidate(LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI) {
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// Invalidate all block entries.
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++Tag;
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// Invalidate all iterators.
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PrevPos = SlotIndex();
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unsigned i = 0;
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i)
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RegUnits[i].VirtTag = LIUArray[*Units].getTag();
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}
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void InterferenceCache::Entry::reset(unsigned physReg,
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LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI,
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const MachineFunction *MF) {
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assert(!hasRefs() && "Cannot reset cache entry with references");
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// LIU's changed, invalidate cache.
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++Tag;
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PhysReg = physReg;
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Blocks.resize(MF->getNumBlockIDs());
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// Reset iterators.
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PrevPos = SlotIndex();
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RegUnits.clear();
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units) {
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RegUnits.push_back(LIUArray[*Units]);
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RegUnits.back().Fixed = &LIS->getRegUnit(*Units);
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}
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}
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bool InterferenceCache::Entry::valid(LiveIntervalUnion *LIUArray,
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const TargetRegisterInfo *TRI) {
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unsigned i = 0, e = RegUnits.size();
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for (MCRegUnitIterator Units(PhysReg, TRI); Units.isValid(); ++Units, ++i) {
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if (i == e)
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return false;
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if (LIUArray[*Units].changedSince(RegUnits[i].VirtTag))
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return false;
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}
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return i == e;
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}
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void InterferenceCache::Entry::update(unsigned MBBNum) {
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SlotIndex Start, Stop;
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std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
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// Use advanceTo only when possible.
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if (PrevPos != Start) {
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if (!PrevPos.isValid() || Start < PrevPos) {
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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RegUnitInfo &RUI = RegUnits[i];
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RUI.VirtI.find(Start);
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RUI.FixedI = RUI.Fixed->find(Start);
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}
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} else {
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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RegUnitInfo &RUI = RegUnits[i];
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RUI.VirtI.advanceTo(Start);
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if (RUI.FixedI != RUI.Fixed->end())
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RUI.FixedI = RUI.Fixed->advanceTo(RUI.FixedI, Start);
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}
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}
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PrevPos = Start;
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}
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MachineFunction::const_iterator MFI = MF->getBlockNumbered(MBBNum);
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BlockInterference *BI = &Blocks[MBBNum];
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ArrayRef<SlotIndex> RegMaskSlots;
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ArrayRef<const uint32_t*> RegMaskBits;
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for (;;) {
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BI->Tag = Tag;
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BI->First = BI->Last = SlotIndex();
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// Check for first interference from virtregs.
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
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if (!I.valid())
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continue;
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SlotIndex StartI = I.start();
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if (StartI >= Stop)
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continue;
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if (!BI->First.isValid() || StartI < BI->First)
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BI->First = StartI;
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}
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// Same thing for fixed interference.
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveInterval::const_iterator I = RegUnits[i].FixedI;
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LiveInterval::const_iterator E = RegUnits[i].Fixed->end();
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if (I == E)
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continue;
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SlotIndex StartI = I->start;
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if (StartI >= Stop)
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continue;
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if (!BI->First.isValid() || StartI < BI->First)
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BI->First = StartI;
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}
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// Also check for register mask interference.
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RegMaskSlots = LIS->getRegMaskSlotsInBlock(MBBNum);
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RegMaskBits = LIS->getRegMaskBitsInBlock(MBBNum);
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SlotIndex Limit = BI->First.isValid() ? BI->First : Stop;
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for (unsigned i = 0, e = RegMaskSlots.size();
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i != e && RegMaskSlots[i] < Limit; ++i)
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if (MachineOperand::clobbersPhysReg(RegMaskBits[i], PhysReg)) {
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// Register mask i clobbers PhysReg before the LIU interference.
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BI->First = RegMaskSlots[i];
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break;
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}
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PrevPos = Stop;
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if (BI->First.isValid())
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break;
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// No interference in this block? Go ahead and precompute the next block.
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if (++MFI == MF->end())
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return;
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MBBNum = MFI->getNumber();
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BI = &Blocks[MBBNum];
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if (BI->Tag == Tag)
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return;
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std::tie(Start, Stop) = Indexes->getMBBRange(MBBNum);
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}
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// Check for last interference in block.
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveIntervalUnion::SegmentIter &I = RegUnits[i].VirtI;
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if (!I.valid() || I.start() >= Stop)
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continue;
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I.advanceTo(Stop);
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bool Backup = !I.valid() || I.start() >= Stop;
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if (Backup)
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--I;
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SlotIndex StopI = I.stop();
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if (!BI->Last.isValid() || StopI > BI->Last)
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BI->Last = StopI;
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if (Backup)
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++I;
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}
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// Fixed interference.
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for (unsigned i = 0, e = RegUnits.size(); i != e; ++i) {
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LiveInterval::iterator &I = RegUnits[i].FixedI;
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LiveRange *LR = RegUnits[i].Fixed;
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if (I == LR->end() || I->start >= Stop)
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continue;
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I = LR->advanceTo(I, Stop);
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bool Backup = I == LR->end() || I->start >= Stop;
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if (Backup)
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--I;
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SlotIndex StopI = I->end;
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if (!BI->Last.isValid() || StopI > BI->Last)
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BI->Last = StopI;
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if (Backup)
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++I;
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}
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// Also check for register mask interference.
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SlotIndex Limit = BI->Last.isValid() ? BI->Last : Start;
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for (unsigned i = RegMaskSlots.size();
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i && RegMaskSlots[i-1].getDeadSlot() > Limit; --i)
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if (MachineOperand::clobbersPhysReg(RegMaskBits[i-1], PhysReg)) {
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// Register mask i-1 clobbers PhysReg after the LIU interference.
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// Model the regmask clobber as a dead def.
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BI->Last = RegMaskSlots[i-1].getDeadSlot();
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break;
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}
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}
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