Matt Arsenault 8b3a9205b7 R600/SI: Also try to use 0 base for misaligned 8-byte DS loads. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@219823 91177308-0d34-0410-b5e6-96231b3b80d8		2014-10-15 18:06:43 +00:00
..
AArch64	Revert "[FastISel][AArch64] Add custom lowering for GEPs."	2014-10-15 04:55:48 +00:00
ARM	ARM: remove ARM/Thumb distinction for preferred alignment.	2014-10-14 22:12:17 +00:00
CPP
Generic	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Hexagon	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Inputs	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Mips	[mips] Mark redundant instructions with a comment in test/CodeGen/Mips/Fast-ISel/icmpa.ll.	2014-10-13 10:18:02 +00:00
MSP430	Drop the W postfix on the 16-bit registers.	2014-09-10 06:58:14 +00:00
NVPTX	[MachineSink] Use the real post dominator tree	2014-10-15 03:27:43 +00:00
PowerPC	Improve sqrt estimate algorithm (fast-math)	2014-10-09 21:26:35 +00:00
R600	R600/SI: Also try to use 0 base for misaligned 8-byte DS loads.	2014-10-15 18:06:43 +00:00
SPARC	Add back tests for empty function in SPARC and PowerPC.	2014-09-15 22:11:07 +00:00
SystemZ
Thumb	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00
Thumb2	[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5	2014-10-01 13:13:18 +00:00
X86	[MachineSink] Use the real post dominator tree	2014-10-15 03:27:43 +00:00
XCore	Revert "Revert "DI: Fold constant arguments into a single MDString""	2014-10-03 20:01:09 +00:00