Erik Eckstein 8b4cc5e616 Revert r231276 (including r231277): Add a lock() function in PassRegistry to speed up multi-thread synchronization. ... git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231385 91177308-0d34-0410-b5e6-96231b3b80d8		2015-03-05 17:53:00 +00:00
..
Analysis	Reformat.	2015-03-05 01:25:19 +00:00
AsmParser
Bitcode
CodeGen	[DagCombiner] Allow shuffles to merge through bitcasts	2015-03-05 17:14:04 +00:00
DebugInfo	DWARFFormValue: Add getAsSignedConstant method.	2015-03-04 22:07:41 +00:00
ExecutionEngine	Make DataLayout Non-Optional in the Module	2015-03-04 18:43:29 +00:00
Fuzzer
IR	Revert r231276 (including r231277): Add a lock() function in PassRegistry to speed up multi-thread synchronization.	2015-03-05 17:53:00 +00:00
IRReader
LineEditor
Linker	Make DataLayout Non-Optional in the Module	2015-03-04 18:43:29 +00:00
LTO	Make DataLayout Non-Optional in the Module	2015-03-04 18:43:29 +00:00
MC	Expand variables when evaluating absolute expressions.	2015-03-04 22:03:21 +00:00
Object	Make DataLayout Non-Optional in the Module	2015-03-04 18:43:29 +00:00
Option
ProfileData
Support	[Windows] Implement PrintStackTrace(FILE*)	2015-03-05 17:47:52 +00:00
TableGen
Target	While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics.	2015-03-05 16:24:38 +00:00
Transforms	[InstCombine] Fix an assertion when fmul has a ConstantExpr operand	2015-03-05 08:38:57 +00:00
CMakeLists.txt
LLVMBuild.txt
Makefile