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https://github.com/c64scene-ar/llvm-6502.git
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a6425604c2
insertions. The old behavior could cause arbitrarily bad memory usage in the DAG combiner if there was heavy traffic of adding nodes already on the worklist to it. This commit switches the DAG combine worklist to work the same way as the instcombine worklist where we null-out removed entries and only add new entries to the worklist. My measurements of codegen time shows slight improvement. The memory utilization is unsurprisingly dominated by other factors (the IR and DAG itself I suspect). This change results in subtle, frustrating churn in the particular order in which DAG combines are applied which causes a number of minor regressions where we fail to match a pattern previously matched by accident. AFAICT, all of these should be using AddToWorklist to directly or should be written in a less brittle way. None of the changes seem drastically bad, and a few of the changes seem distinctly better. A major change required to make this work is to significantly harden the way in which the DAG combiner handle nodes which become dead (zero-uses). Previously, we relied on the ability to "priority-bump" them on the combine worklist to achieve recursive deletion of these nodes and ensure that the frontier of remaining live nodes all were added to the worklist. Instead, I've introduced a routine to just implement that precise logic with no indirection. It is a significantly simpler operation than that of the combiner worklist proper. I suspect this will also fix some other problems with the combiner. I think the x86 changes are really minor and uninteresting, but the avx512 change at least is hiding a "regression" (despite the test case being just noise, not testing some performance invariant) that might be looked into. Not sure if any of the others impact specific "important" code paths, but they didn't look terribly interesting to me, or the changes were really minor. The consensus in review is to fix any regressions that show up after the fact here. Thanks to the other reviewers for checking the output on other architectures. There is a specific regression on ARM that Tim already has a fix prepped to commit. Differential Revision: http://reviews.llvm.org/D4616 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@213727 91177308-0d34-0410-b5e6-96231b3b80d8
169 lines
4.0 KiB
LLVM
169 lines
4.0 KiB
LLVM
; rdar://7860110
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; RUN: llc -asm-verbose=false < %s | FileCheck %s -check-prefix=X64
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; RUN: llc -march=x86 -asm-verbose=false < %s | FileCheck %s -check-prefix=X32
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
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target triple = "x86_64-apple-darwin10.2"
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define void @test1(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, -256 ; 0xFFFFFF00
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%C = zext i8 %a1 to i32
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%D = or i32 %C, %B
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store i32 %D, i32* %a0, align 4
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ret void
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; X64-LABEL: test1:
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; X64: movb %sil, (%rdi)
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; X32-LABEL: test1:
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; X32: movb 8(%esp), %al
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; X32: movb %al, (%{{.*}})
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}
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define void @test2(i32* nocapture %a0, i8 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, -65281 ; 0xFFFF00FF
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%C = zext i8 %a1 to i32
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%CS = shl i32 %C, 8
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%D = or i32 %B, %CS
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store i32 %D, i32* %a0, align 4
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ret void
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; X64-LABEL: test2:
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; X64: movb %sil, 1(%rdi)
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; X32-LABEL: test2:
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; X32: movzbl 8(%esp), %e[[REG:[abcd]]]x
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; X32: movb %[[REG]]l, 1(%{{.*}})
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}
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define void @test3(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, -65536 ; 0xFFFF0000
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%C = zext i16 %a1 to i32
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%D = or i32 %B, %C
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store i32 %D, i32* %a0, align 4
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ret void
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; X64-LABEL: test3:
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; X64: movw %si, (%rdi)
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; X32-LABEL: test3:
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; X32: movw 8(%esp), %ax
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; X32: movw %ax, (%{{.*}})
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}
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define void @test4(i32* nocapture %a0, i16 zeroext %a1) nounwind ssp {
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entry:
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%A = load i32* %a0, align 4
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%B = and i32 %A, 65535 ; 0x0000FFFF
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%C = zext i16 %a1 to i32
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%CS = shl i32 %C, 16
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%D = or i32 %B, %CS
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store i32 %D, i32* %a0, align 4
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ret void
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; X64-LABEL: test4:
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; X64: movw %si, 2(%rdi)
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; X32-LABEL: test4:
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; X32: movl 8(%esp), %e[[REG:[abcd]x]]
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; X32: movw %[[REG]], 2(%{{.*}})
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}
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define void @test5(i64* nocapture %a0, i16 zeroext %a1) nounwind ssp {
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entry:
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%A = load i64* %a0, align 4
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%B = and i64 %A, -4294901761 ; 0xFFFFFFFF0000FFFF
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%C = zext i16 %a1 to i64
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%CS = shl i64 %C, 16
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%D = or i64 %B, %CS
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store i64 %D, i64* %a0, align 4
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ret void
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; X64-LABEL: test5:
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; X64: movw %si, 2(%rdi)
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; X32-LABEL: test5:
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; X32: movzwl 8(%esp), %e[[REG:[abcd]x]]
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; X32: movw %[[REG]], 2(%{{.*}})
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}
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define void @test6(i64* nocapture %a0, i8 zeroext %a1) nounwind ssp {
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entry:
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%A = load i64* %a0, align 4
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%B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF
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%C = zext i8 %a1 to i64
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%CS = shl i64 %C, 40
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%D = or i64 %B, %CS
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store i64 %D, i64* %a0, align 4
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ret void
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; X64-LABEL: test6:
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; X64: movb %sil, 5(%rdi)
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; X32-LABEL: test6:
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; X32: movb 8(%esp), %[[REG:[abcd]l]]
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; X32: movb %[[REG]], 5(%{{.*}})
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}
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define i32 @test7(i64* nocapture %a0, i8 zeroext %a1, i32* %P2) nounwind {
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entry:
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%OtherLoad = load i32 *%P2
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%A = load i64* %a0, align 4
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%B = and i64 %A, -280375465082881 ; 0xFFFF00FFFFFFFFFF
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%C = zext i8 %a1 to i64
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%CS = shl i64 %C, 40
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%D = or i64 %B, %CS
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store i64 %D, i64* %a0, align 4
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ret i32 %OtherLoad
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; X64-LABEL: test7:
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; X64: movb %sil, 5(%rdi)
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; X32-LABEL: test7:
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; X32: movb 8(%esp), %[[REG:[abcd]l]]
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; X32: movb %[[REG]], 5(%{{.*}})
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}
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; PR7833
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@g_16 = internal global i32 -1
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; X64-LABEL: test8:
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; X64-NEXT: movl _g_16(%rip), %eax
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; X64-NEXT: movl $0, _g_16(%rip)
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; X64-NEXT: orl $1, %eax
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; X64-NEXT: movl %eax, _g_16(%rip)
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; X64-NEXT: ret
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define void @test8() nounwind {
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%tmp = load i32* @g_16
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store i32 0, i32* @g_16
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%or = or i32 %tmp, 1
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store i32 %or, i32* @g_16
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ret void
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}
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; X64-LABEL: test9:
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; X64-NEXT: orb $1, _g_16(%rip)
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; X64-NEXT: ret
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define void @test9() nounwind {
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%tmp = load i32* @g_16
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%or = or i32 %tmp, 1
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store i32 %or, i32* @g_16
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ret void
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}
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; rdar://8494845 + PR8244
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; X64-LABEL: test10:
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; X64-NEXT: movsbl (%rdi), %eax
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; X64-NEXT: shrl $8, %eax
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; X64-NEXT: ret
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define i8 @test10(i8* %P) nounwind ssp {
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entry:
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%tmp = load i8* %P, align 1
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%conv = sext i8 %tmp to i32
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%shr3 = lshr i32 %conv, 8
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%conv2 = trunc i32 %shr3 to i8
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ret i8 %conv2
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}
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